Multiple serial access memory for use in feedback systems such as motion compensated television

Claim 2

A multiple serial access memory comprising: a dynamic random access memory array P rows high by Q columns wide by B bits deep; means for addressing said array to randomly input N row high by M column wide blocks of B bit data bytes thereto, where N<P and M<Q; means for outputting rows of data of length L from said array in response to address signals provided by said addressing means, where M<L<Q; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; and means for clocking said serial output ports to output latched data therefrom.

Claim 3

A memory in accordance with claim 1 further comprising: timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.

Claim 4

A memory in accordance with claim 1 wherein each of said serial output ports comprises: a shift register having a length at least equal to a width of said array, said shift register being responsive to a first signal from a timing means for latching a row of data from said array and responsive to a second signal from said timing means for shifting the row of latched data; and a serial access selector coupled to said shift register for outputting a selected portion of the shifted data from the serial output port.

Claim 5

In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising: a dynamic random access memory array P rows high by Q columns wide by B bits deep; means for addressing said array to randomly input N row high by M column wide blocks of B bit data bytes thereto, where N<P and M<Q; means for outputting rows of data of length L from said array in response to address signals provided by said addressing means, where M<L<Q; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; and means for clocking said serial output ports to output latched data therefrom; wherein at least one of said serial output ports is used to output working data from said array and at least one other of said serial output ports is used to output display data from said array.

Claim 6

In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising: a dynamic random access memory array P rows high by Q columns wide by B bits deep; means for addressing said array to randomly input N row high by M column wide blocks of B bit data bytes thereto, where N<P and M<Q; means for outputting rows of data of length L from said array in response to address signals provided by said addressing means, where M<L<Q; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; and means for clocking said serial output ports to output latched data therefrom; wherein at least one of said serial output ports is used to output working data from said array and at least one other of said serial output ports is used to output display data from said array.

Claim 7

Television apparatus in accordance with claim 4 further comprising: timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.

Claim 8

Television apparatus in accordance with claim 4 wherein each of said serial output ports comprises: a shift register having a length at least equal to a width of said array, said shift register being responsive to a first signal from a timing means for latching a row of data from said array and responsive to a second signal from said timing means for shifting the row of latched data; and a serial access selector coupled to said shift register for outputting a selected portion of the shifted data from the serial output port.

Claim 9

Television apparatus in accordance with claim 4 wherein: said working data is provided from the array to its respective serial output port in one of a field format and frame format; and said display data is provided from the array to its respective serial output port in the other of said field format and frame format.

Claim 10

Television apparatus in accordance with claim 4 wherein: said working data is provided from the array to its respective serial output port in an NxM block format, where N is a plurality of television lines and M is a number of pixels less than the number of pixels contained in a full television line; and said display data is provided from the array to its respective serial output port in a television line format.

Claim 11

Television apparatus in accordance with claim 4 wherein: said display data comprises pixel data for a current video frame; said working data comprises pixel data from a previous video frame for use in reconstructing a current video frame from a motion compensation difference signal; said array has a storage capacity sufficient to store said current video frame together with enough working data to accommodate a predetermined motion estimation search area; and said array is filled with data for successive video frames on an ongoing basis with the data for a current frame overwriting a portion of the data for a previous frame that precedes a current motion estimation search area.

Claim 14

A multiple serial access memory comprising: a dynamic random access memory array; means for addressing said array to input data thereto and output data therefrom; means for outputting rows of data from said array in response to address signals provided by said addressing means; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; and means for clocking said serial output ports to output latched data therefrom; wherein each of said serial output ports comprises: a shift register having a length at least equal to a width of said array, said shift register being responsive to a first signal from a timing means for latching a row of data from said array and responsive to a second signal from said timing means for shifting the row of latched data; and a serial access selector coupled to said shift register for outputting a selected portion of the shifted data from the serial output port.

Claim 15

A multiple serial access memory comprising: a dynamic random access memory array; means for addressing said array to input data thereto and output data therefrom; means for outputting rows of data from said array in response to address signals provided by said addressing means; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; and means for clocking said serial output ports to output latched data therefrom; wherein each of said serial output ports comprises: a shift register having a length at least equal to a width of said array, said shift register being responsive to a first signal from a timing means for latching a row of data from said array and responsive to a second signal from said timing means for shifting the row of latched data; and a serial access selector coupled to said shift register for outputting a selected portion of the shifted data from the serial output port.

Claim 16

A memory in accordance with claim 11 further comprising: timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.

Claim 17

In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising: a dynamic random access memory array; means for addressing said array to input data thereto and output data therefrom; means for outputting rows of data from said array in response to address signals provided by said addressing means; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; and means for clocking said serial output ports to output latched data therefrom; wherein at least one of said serial output ports is used to output working data from said array and at least one other of said serial output ports is used to output display data from said array and each of said serial output ports comprises: a shift register having a length at least equal to a width of said array, said shift register being responsive to a first signal from a timing means for latching a row of data from said array and responsive to a second signal from said timing means for shifting the row of latched data; and a serial access selector coupled to said shift register for outputting a selected portion of the shifted data from the serial output port.

Claim 18

In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising: a dynamic random access memory array; means for addressing said array to input data thereto and output data therefrom; means for outputting rows of data from said array in response to address signals provided by said addressing means; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; and means for clocking said serial output ports to output latched data therefrom; wherein at least one of said serial output ports is used to output working data from said array and at least one other of said serial output ports is used to output display data from said array and each of said serial output ports comprises: a shift register having a length at least equal to a width of said array, said shift register being responsive to a first signal from a timing means for latching a row of data from said array and responsive to a second signal from said timing means for shifting the row of latched data; and a serial access selector coupled to said shift register for outputting a selected portion of the shifted data from the serial output port.

Claim 19

A memory in accordance with claim 13 further comprising: timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.

Claim 20

In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising: a dynamic random access memory array; means for addressing said array to input data thereto and output data therefrom; means for outputting rows of data from said array in response to address signals provided by said addressing means; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; means for clocking said serial output ports to output latched data therefrom; at least one of said serial output ports being used to output working data from said array; and at least one other of said serial output ports being used to output display data from said array; wherein: said working data is provided from the array to its respective serial output port in one of a field format and frame format; and said display data is provided from the array to its respective serial output port in the other of said field format and frame format.

Claim 21

In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising: a dynamic random access memory array; means for addressing said array to input data thereto and output data therefrom; means for outputting rows of data from said array in response to address signals provided by said addressing means; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; means for clocking said serial output ports to output latched data therefrom; at least one of said serial output ports being used to output working data from said array; and at least one other of said serial output ports being used to output display data from said array; wherein: said working data is provided from the array to its respective serial output port in one of a field format and frame format; and said display data is provided from the array to its respective serial output port in the other of said field format and frame format.

Claim 22

A memory in accordance with claim 15 further comprising: timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.

Claim 23

In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising: a dynamic random access memory array; means for addressing said array to input data thereto and output data therefrom; means for outputting rows of data from said array in response to address signals provided by said addressing means; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; means for clocking said serial output ports to output latched data therefrom; at least one of said serial output ports being used to output working data from said array; and at least one other of said serial output ports being used to output display data from said array; wherein: said working data is provided from the array to its respective serial output port in an NxM block format, where N is a plurality of television lines and M is a number of pixels less than the number of pixels contained in a full television line; and said display data is provided from the array to its respective serial output port in a television line format.

Claim 24

In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising: a dynamic random access memory array; means for addressing said array to input data thereto and output data therefrom; means for outputting rows of data from said array in response to address signals provided by said addressing means; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; means for clocking said serial output ports to output latched data therefrom; at least one of said serial output ports being used to output working data from said array; and at least one other of said serial output ports being used to output display data from said array; wherein: said working data is provided from the array to its respective serial output port in an NxM block format, where N is a plurality of television lines and M is a number of pixels less than the number of pixels contained in a full television line; and said display data is provided from the array to its respective serial output port in a television line format.

Claim 25

A memory in accordance with claim 17 further comprising: timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.

Claim 26

In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising: a dynamic random access memory array; means for addressing said array to input data thereto and output data therefrom; means for outputting rows of data from said array in response to address signals provided by said addressing means; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; means for clocking said serial output ports to output latched data therefrom; at least one of said serial output ports being used to output working data from said array; and at least one other of said serial output ports being used to output display data from said array; wherein: said display data comprises pixel data for a current video frame; said working data comprises pixel data from a previous video frame for use in reconstructing a current video frame from a motion compensation difference signal; said array has a storage capacity sufficient to store said current video frame together with enough working data to accommodate a predetermined motion estimation search area; and said array is filled with data for successive video frames on an ongoing basis with the data for a current frame overwriting a portion of the data for a previous frame that precedes a current motion estimation search area.

Claim 27

In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising: a dynamic random access memory array; means for addressing said array to input data thereto and output data therefrom; means for outputting rows of data from said array in response to address signals provided by said addressing means; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; means for clocking said serial output ports to output latched data therefrom; at least one of said serial output ports being used to output working data from said array; and at least one other of said serial output ports being used to output display data from said array; wherein: said display data comprises pixel data for a current video frame; said working data comprises pixel data from a previous video frame for use in reconstructing a current video frame from a motion compensation difference signal; said array has a storage capacity sufficient to store said current video frame together with enough working data to accommodate a predetermined motion estimation search area; and said array is filled with data for successive video frames on an ongoing basis with the data for a current frame overwriting a portion of the data for a previous frame that precedes a current motion estimation search area.

Claim 28

A memory in accordance with claim 19 further comprising: timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.