Semiconductor memory device having a plurality of access ports

Claim 1

A semiconductor memory device comprising a memory array of a plurality of memory cells arranged in a matrix form of rows and columns, means for selecting one of said rows thereby the enable the memory cells of the selected row for writing data thereto or reading data therefrom through said columns, a random access circuit coupled to said columns of said memory array for performing a random selection of said columns for reading data therefrom or writing data thereto in response to column address information, a first clock input terminal for receiving a first chain of clock signals, a second clock input terminal for receiving a second chain of clock signals, a serial output terminal, a serial output circuit coupled to said serial output terminal and said columns of said memory array for sequentially outputting at said serial output terminal data from said columns one by one in synchronism with said first chain of clock signals, a serial input terminal, an input register having a plurality of storage locations, a serial input circuit coupled to said serial input terminal and said input register for sequentially writing data applied to said serial input terminal to said input register one by one in synchronism with said second chain of clock signals, and a write circuit for operatively writing data stored in said input register to said columns in parallel simultaneously.