US5513327A
Expired / Lapsed
US
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Integrated circuit I/O using a high performance bus interface
Assignee: Rambus Inc
•
Filing: 1994-03-31
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Granted: 1996-04-30
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Expires: 2014-03-31
Abstract
Abstract A dynamic random access memory (DRAM). The DRAM comprises a first circuit for providing a clock signal and a conductor for coupling the DRAM to a bus. A receiver circuit is coupled to the conductor and the first circuit for latching information received from the conductor in response to detecting each of a rising edge of the clock signal and a falling edge of the clock signal. The receiver circuit may include a first input receiver for latching information in response to the rising edge of the clock signal and a second input receiver for latching information in response to the falling edge of the clock signal.
Inventors
- 👤 Michael Farmwald
- 👤 Mark Horowitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:17
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G06; G06F; G06F11/00; G06F11/006; G06F12/00; G06F12/02; G06F12/0215; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F12/0684; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1668; G06F13/1678; G06F13/1689; G06F13/1694; G06F13/36; G06F13/368; G06F13/376; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4096; G11C29/00; G11C29/70; G11C29/88; G11C5/00; G11C5/02; G11C5/04; G11C5/06; G11C5/063; G11C5/066; G11C7/1006; G11C7/1012; G11C7/1015; G11C7/1045; G11C7/1057; G11C7/1069; G11C7/1072; G11C7/1078; G11C7/1084; G11C7/22; G11C7/222; G11C7/225; G11C8/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G11C2207/00; G11C2207/10; G11C2207/105; G11C2207/108; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
138 words
A dynamic random access memory (DRAM), comprising: a first circuit for providing a clock signal: a conductor for coupling the DRAM to a bus; and a receiver circuit coupled to the conductor and the first circuit, the receiver circuit for latching information received from the conductor in response to a rising edge of the clock signal and a falling edge of the clock signal, wherein the receiver circuit comprises: a first input receiver coupled to the conductor and the first circuit, the first input receiver for latching information provided by the bus via the conductor in response to the rising edge of the clock signal; and a second input receiver coupled to the conductor and the first circuit, the second input receiver for latching information from the bus in response to the falling edge of the clock signal.
Claim 2
Dependent Claim
138 words
A dynamic random access memory (DRAM), comprising: a first circuit for providing a clock signal: a conductor for coupling the DRAM to a bus; and a receiver circuit coupled to the conductor and the first circuit, the receiver circuit for latching information received from the conductor in response to a rising edge of the clock signal and a falling edge of the clock signal, wherein the receiver circuit comprises: a first input receiver coupled to the conductor and the first circuit, the first input receiver for latching information provided by the bus via the conductor in response to the rising edge of the clock signal; and a second input receiver coupled to the conductor and the first circuit, the second input receiver for latching information from the bus in response to the falling edge of the clock signal.
Claim 3
Dependent Claim
90 words
The DRAM of claim 1, wherein the first circuit provides a first clock signal and a second clock signal that is a complement of the first clock signal, the first input receiver being coupled to receive the first clock signal such that the first input receiver latches information in response to a rising edge of the first clock signal, the second input receiver being coupled to receive the second clock signal such that the second input receiver latches information in response to a rising edge of the second clock signal.
Claim 4
Dependent Claim
24 words
The DRAM of claim 2, wherein the first circuit provides the first and second clock signals in response to an externally provided clock signal.
Claim 5
Dependent Claim
21 words
The DRAM of claim 1, wherein the first circuit provides the clock signal in response to an externally provided clock signal.
Claim 6
Dependent Claim
139 words
The DRAM of claim 1, wherein the DRAM further comprises: a multiplexer coupled to the first circuit, the multiplexer having an output, a first input, and a second input; an output driver including an output coupled to the conductor and an input coupled to the output of the multiplexer, the output driver for driving data on the conductor in response to the output of the multiplexer; a first output line coupled to the first input of the multiplexer, wherein the multiplexer couples the first output line to the output of the multiplexer in response to the rising edge of the clock signal; and a second output line coupled to the second input of the multiplexer, wherein the multiplexer couples the second output line to the output of the multiplexer in response to the falling edge of the clock signal.
Claim 7
Dependent Claim
59 words
The DRAM of claim 5, wherein the output driver is a field effect transistor including a drain coupled to the conductor, a source coupled to system ground, and a gate coupled to output of the multiplexer, the field effect transistor being switched on and off in response to a state of a selected output line provided by the multiplexer.
Claim 8
Dependent Claim
153 words
A dynamic random access memory (DRAM), comprising: a first circuit for providing a clock signal; a conductor for coupling the DRAM to a bus; a multiplexer coupled to the first circuit, the multiplexer having an output, a first input, and a second input; an output driver including an output coupled to the conductor and an input coupled to the output of the multiplexer, the output driver for driving data on the conductor in response to the output of the multiplexer; a first output line coupled to the first input of the multiplexer, wherein the multiplexer couples the first output line to the output of the multiplexer in response to a rising edge of the clock signal; and a second output line coupled to the second input of the multiplexer, wherein the multiplexer couples the second output line to the output of the multiplexer in response to a falling edge of the clock signal.
Claim 9
Dependent Claim
153 words
A dynamic random access memory (DRAM), comprising: a first circuit for providing a clock signal; a conductor for coupling the DRAM to a bus; a multiplexer coupled to the first circuit, the multiplexer having an output, a first input, and a second input; an output driver including an output coupled to the conductor and an input coupled to the output of the multiplexer, the output driver for driving data on the conductor in response to the output of the multiplexer; a first output line coupled to the first input of the multiplexer, wherein the multiplexer couples the first output line to the output of the multiplexer in response to a rising edge of the clock signal; and a second output line coupled to the second input of the multiplexer, wherein the multiplexer couples the second output line to the output of the multiplexer in response to a falling edge of the clock signal.
Claim 10
Dependent Claim
59 words
The DRAM of claim 7, wherein the output driver is a field effect transistor including a drain coupled to the conductor, a source coupled to system ground, and a gate coupled to output of the multiplexer, the field effect transistor being switched on and off in response to a state of a selected output line provided by the multiplexer.
Claim 11
Dependent Claim
154 words
A memory storage system comprising: a bus for transferring information; a first dynamic random access memory (DRAM) coupled to the bus, the first DRAM comprising: a first circuit for providing a clock signal; a conductor for coupling the DRAM to the bus; a receiver circuit coupled to the conductor and the first circuit, the receiver circuit for latching information received from the conductor in response to a rising edge of the clock signal and a falling edge of the clock signal; the receiver circuit comprising: a first input receiver coupled to the conductor and the first circuit, the first input receiver for latching information provided by the bus via the conductor in response to the rising edge of the clock signal; and a second input receiver coupled to the conductor and the first circuit, the second input receiver for latching information from the bus in response to the falling edge of the clock signal.
Claim 12
Dependent Claim
154 words
A memory storage system comprising: a bus for transferring information; a first dynamic random access memory (DRAM) coupled to the bus, the first DRAM comprising: a first circuit for providing a clock signal; a conductor for coupling the DRAM to the bus; a receiver circuit coupled to the conductor and the first circuit, the receiver circuit for latching information received from the conductor in response to a rising edge of the clock signal and a falling edge of the clock signal; the receiver circuit comprising: a first input receiver coupled to the conductor and the first circuit, the first input receiver for latching information provided by the bus via the conductor in response to the rising edge of the clock signal; and a second input receiver coupled to the conductor and the first circuit, the second input receiver for latching information from the bus in response to the falling edge of the clock signal.
Claim 13
Dependent Claim
92 words
The memory storage system of claim 9, wherein the first circuit provides a first clock signal and a second clock signal that is a complement of the first clock signal, the first input receiver being coupled to receive the first clock signal such that the first input receiver latches information in response to a rising edge of the first clock signal, the second input receiver being coupled to receive the second clock signal such that the second input receiver latches information in response to a rising edge of the second clock signal.
Claim 14
Dependent Claim
52 words
The memory storage system of claim 10, wherein the memory storage system further includes a third circuit for providing a system clock signal, the first circuit being coupled to receive the system clock signal, the first circuit for providing the first and second clock signals in response to a system clock signal.
Claim 15
Dependent Claim
63 words
The memory storage system of claim 9, wherein the memory storage system further includes a third circuit for providing a system clock signal, the first circuit being coupled to receive the system clock signal, the first circuit for providing a first clock signal and a second clock signal that is a complement of the first clock in response to the system clock signal.
Claim 16
Dependent Claim
89 words
The memory storage system of claim 12, wherein a bus cycle for the bus is divided into an even cycle corresponding to a rising edge of the system clock signal and an odd cycle corresponding to a falling edge of the system clock signal, the memory storage system further comprising: a master coupled to the bus and the third circuit, the master for transferring information to and from the DRAM via the bus, the master for signaling the beginning of an operation to the DRAM only on even cycles.
Claim 17
Dependent Claim
13 words
The memory storage system of claim 13, wherein the master is a processor.
Claim 18
Dependent Claim
89 words
The memory storage system of claim 12, wherein a bus cycle for the bus is divided into an even cycle corresponding to a falling edge of the system clock signal and an odd cycle corresponding to a rising edge of the system clock signal, the memory storage system further comprising: a master coupled to the bus and the third circuit, the master for transferring information to and from the DRAM via the bus, the master for signaling the beginning of an operation to the DRAM only on even cycles.
Claim 19
Dependent Claim
141 words
The memory storage system of claim 9, wherein the DRAM further comprises: a multiplexer coupled to the first circuit, the multiplexer having an output, a first input, and a second input; an output driver including an output coupled to the conductor and an input coupled to the output of the multiplexer, the output driver for driving data on the conductor in response to the output of the multiplexer; a first output line coupled to the first input of the multiplexer, wherein the multiplexer couples the first output line to the output of the multiplexer in response to the rising edge of the clock signal; and a second output line coupled to the second input of the multiplexer, wherein the multiplexer couples the second output line to the output of the multiplexer in response to the falling edge of the clock signal.
Claim 20
Dependent Claim
61 words
The memory storage system of claim 16, wherein the output driver is a field effect transistor including a drain coupled to the conductor, a source coupled to system ground, and a gate coupled to output of the multiplexer, the field effect transistor being switched on and off in response to a state of a selected output line provided by the multiplexer.
Claim 21
Dependent Claim
171 words
A memory storage system comprising: a bus for transferring information; a first dynamic random access memory (DRAM) coupled to the bus, the first DRAM comprising: a first circuit for providing a clock signal; a conductor for coupling the DRAM to the bus; a multiplexer coupled to the first circuit, the multiplexer having an output, a first input, and a second input; an output driver including an output coupled to the conductor and an input coupled to the output of the multiplexer, the output driver for driving data on the conductor in response to the output of the multiplexer; a first output line coupled to the first input of the multiplexer, wherein the multiplexer couples the first output line to the output of the multiplexer in response to a rising edge of the clock signal; and a second output line coupled to the second input of the multiplexer, wherein the multiplexer couples the second output line to the output of the multiplexer in response to a falling edge of the clock signal.
Claim 22
Dependent Claim
171 words
A memory storage system comprising: a bus for transferring information; a first dynamic random access memory (DRAM) coupled to the bus, the first DRAM comprising: a first circuit for providing a clock signal; a conductor for coupling the DRAM to the bus; a multiplexer coupled to the first circuit, the multiplexer having an output, a first input, and a second input; an output driver including an output coupled to the conductor and an input coupled to the output of the multiplexer, the output driver for driving data on the conductor in response to the output of the multiplexer; a first output line coupled to the first input of the multiplexer, wherein the multiplexer couples the first output line to the output of the multiplexer in response to a rising edge of the clock signal; and a second output line coupled to the second input of the multiplexer, wherein the multiplexer couples the second output line to the output of the multiplexer in response to a falling edge of the clock signal.
Claim 23
Dependent Claim
59 words
The DRAM of claim 18, wherein the output driver is a field effect transistor including a drain coupled to the conductor, a source coupled to system ground, and a gate coupled to output of the multiplexer, the field effect transistor being switched on and off in response to a state of a selected output line provided by the multiplexer.
Claim 24
Dependent Claim
79 words
The memory storage system of claim 18, wherein the first circuit provides a first clock signal and a second clock signal that is a complement of the first clock signal, the multiplexer being coupled to receive the first and second clock signals such that the first output line is selected in response to a rising edge of the first clock signal and the second output line is selected in response to a rising edge of the second clock signal.
Claim 25
Dependent Claim
52 words
The memory storage system of claim 20, wherein the memory storage system further includes a third circuit for providing a system clock signal, the first circuit being coupled to receive the system clock signal, the first circuit for providing the first and second clock signals in response to a system clock signal.
Claim 26
Dependent Claim
63 words
The memory storage system of claim 18, wherein the memory storage system further includes a third circuit for providing a system clock signal, the first circuit being coupled to receive the system clock signal, the first circuit for providing a first clock signal and a second clock signal that is a complement of the first clock in response to the system clock signal.
Claim 27
Dependent Claim
89 words
The memory storage system of claim 22, wherein a bus cycle for the bus is divided into an even cycle corresponding to a rising edge of the system clock signal and an odd cycle corresponding to a falling edge of the system clock signal, the memory storage system further comprising: a master coupled to the bus and the third circuit, the master for transferring information to and from the DRAM via the bus, the master for signaling the beginning of an operation to the DRAM only on even cycles.
Claim 28
Dependent Claim
13 words
The memory storage system of claim 23, wherein the master is a processor.
Claim 29
Dependent Claim
89 words
The memory storage system of claim 22, wherein a bus cycle for the bus is divided into an even cycle corresponding to a falling edge of the system clock signal and an odd cycle corresponding to a rising edge of the system clock signal, the memory storage system further comprising: a master coupled to the bus and the third circuit, the master for transferring information to and from the DRAM via the bus, the master for signaling the beginning of an operation to the DRAM only on even cycles.
Claim 30
Dependent Claim
88 words
A dynamic random access memory (DRAM), comprising: a first circuit for providing a plurality of phases of a clock signal; a conductor for coupling the DRAM to a bus; and a plurality of input receivers coupled to the conductor and the first circuit, wherein each input receiver is coupled to receive a corresponding one of the plurality of phases of the clock signal such that each input receiver latches information received from the conductor in response to a rising edge of the corresponding phase of the clock signal.
Claim 31
Dependent Claim
88 words
A dynamic random access memory (DRAM), comprising: a first circuit for providing a plurality of phases of a clock signal; a conductor for coupling the DRAM to a bus; and a plurality of input receivers coupled to the conductor and the first circuit, wherein each input receiver is coupled to receive a corresponding one of the plurality of phases of the clock signal such that each input receiver latches information received from the conductor in response to a rising edge of the corresponding phase of the clock signal.
Claim 32
Dependent Claim
26 words
The DRAM of claim 26, wherein the first circuit provides the plurality of phases of the clock signal in response to an externally provided clock signal.
Claim 33
Dependent Claim
132 words
A dynamic random access memory (DRAM), comprising: a first circuit for providing a plurality of phases of a clock signal; a conductor for coupling the DRAM to a bus; a multiplexer coupled to the first circuit, the multiplexer having an output and a plurality of inputs; an output driver including an output coupled to the conductor and an input coupled to the output of the multiplexer, the output driver for driving data on the conductor in response to the output of the multiplexer; and a plurality of output lines coupled to the plurality of inputs of the multiplexer, wherein each output line is coupled to the output of the multiplexer in response to the multiplexer detecting a rising edge of a phase of the clock signal that corresponds to that output line.
Claim 34
Dependent Claim
132 words
A dynamic random access memory (DRAM), comprising: a first circuit for providing a plurality of phases of a clock signal; a conductor for coupling the DRAM to a bus; a multiplexer coupled to the first circuit, the multiplexer having an output and a plurality of inputs; an output driver including an output coupled to the conductor and an input coupled to the output of the multiplexer, the output driver for driving data on the conductor in response to the output of the multiplexer; and a plurality of output lines coupled to the plurality of inputs of the multiplexer, wherein each output line is coupled to the output of the multiplexer in response to the multiplexer detecting a rising edge of a phase of the clock signal that corresponds to that output line.
Claim 35
Dependent Claim
26 words
The DRAM of claim 28, wherein the first circuit provides the plurality of phases of the clock signal in response to an externally provided clock signal.
References Cited (Backward Citations)
US3721838A
Cited
US3740723A
Cited
US3771145A
Cited
US3771145B1
Cited
US3924241A
Cited
US3758761A
Cited
US3753244A
Cited
US3821715A
Cited
US3983537A
Cited
US3975714A
Cited
US3972028A
Cited
US3882470A
Cited
US4038648A
Cited
US3969706A
Cited
US4007452A
Cited
US4099231A
Cited
US4250570A
Cited
US4250570B1
Cited
US4333142A
Cited
US4191996A
Cited
US4247817A
Cited
US4205373A
Cited
US4315308A
Cited
US4249247A
Cited
US4286321A
Cited
US4306298A
Cited
US4443864A
Cited
US4468738A
Cited
US4373183A
Cited
US4355376A
Cited
US4630193A
Cited
US4500905A
Cited
US4811202A
Cited
US4481625A
Cited
US4595923A
Cited
US4488218A
Cited
US4470114A
Cited
US4449207A
Cited
US4519034A
Cited
US4770640A
Cited
US4649511A
Cited
US4646270A
Cited
US4745548A
Cited
US4654655A
Cited
US4649516A
Cited
US4860198A
Cited
US4933835A
Cited
US4779089A
Cited
US4719627A
Cited
US4706166A
Cited
US4803621A
Cited
US4785394A
Cited
US4818985A
Cited
US4764846A
Cited
US4837682A
Cited
JPH01166545A
Cited
US4975763A
Cited
US5361277A
Cited
US5179670A
Cited
US5023488A
Cited
US5077693A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-30 | 1999-10-30 | 2000-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-30 | 2003-10-30 | 2004-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-30 | 2007-10-30 | 2008-04-30 | $7700.00 | Window Closed / Lapsed |