US4719627A
Expired / Lapsed
US
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Memory system employing a low DC power gate array for error correction
Assignee: Unisys Corp
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Filing: 1986-03-03
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Granted: 1988-01-12
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Expires: 2006-03-03
Abstract
Abstract An error-correcting memory system includes a storage module which receives an address during a read cycle and which reads data bits and check bits at the address, and it further includes a low DC power logic circuit which corrects errors in the data bits by decoding multiple minterms from the check bits; wherein the logic circuit is comprised of: a plurality of logic gates, one for generating each of the minterms by passing a constant power dissipating current to selectively decode the check bits; a control circuit for generating a control signal that is in one state during only a small fraction of the read cycle and is otherwise in an opposite state; and an enabling circuit, coupled between the control circuit and the logic gates, for enabling their selective decoding by permitting the constant current to flow through the gates only while the control signal is in its one state.
Inventors
- 👤 LuVerne R. Peterson
- 👤 Stephen J. Chung Chan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:49
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
177 words
An error-correcting memory system having a storage means which receives an address during a read cycle and which reads data bits and check bits at said address; and a plurality of logic gates which are coupled in parallel to receive input signal, that are derived from said data bits and check bits, for generating multiple minterms therefrom which correct errors in said data bits; wherein: each logic gate generates a respective one of said minterms by passing a constant power dissipating current to selectively decode said input signals only when said input signals are at a certain voltage level; and wherein said memory system also includes, a control means for generating a control signal that is in one state during only a small fraction of said read cycle and is otherwise in an opposite state; and an enabling means, coupled between said control means and said logic gates, for reducing power dissipation in said logic gates by forcing said received input signals out of said certain voltage level whenever said control signal is in said opposite state.
Claim 2
Dependent Claim
177 words
An error-correcting memory system having a storage means which receives an address during a read cycle and which reads data bits and check bits at said address; and a plurality of logic gates which are coupled in parallel to receive input signal, that are derived from said data bits and check bits, for generating multiple minterms therefrom which correct errors in said data bits; wherein: each logic gate generates a respective one of said minterms by passing a constant power dissipating current to selectively decode said input signals only when said input signals are at a certain voltage level; and wherein said memory system also includes, a control means for generating a control signal that is in one state during only a small fraction of said read cycle and is otherwise in an opposite state; and an enabling means, coupled between said control means and said logic gates, for reducing power dissipation in said logic gates by forcing said received input signals out of said certain voltage level whenever said control signal is in said opposite state.
Claim 3
Dependent Claim
58 words
A memory system according to claim 1 and further including a means for forming new check bits from said data bits which are read from said storage means, and wherein said control means forces said control signal into said opposite state throughout said read cycle when said new check bits are the same as said read check bits.
Claim 4
Dependent Claim
41 words
A memory system according to claim 1 wherein said system also includes a write cycle in which data is written into said storage means, and wherein said control means forces said control signal into said opposite state throughout said write cycle.
Claim 5
Dependent Claim
24 words
A memory system according to claim 1 wherein said system further includes multiple OR gates which are coupled to selectively OR said minterms together.
Claim 6
Dependent Claim
145 words
A memory system having a storage means which receives an address during a read cycle and which reads data bits and check bits at said address, and a plurality of logic gates which are coupled in parallel which correct errors in said data bits; wherein: each logic gate generates a respective one of said minterms by passing a constant power dissipating current from a common bus to selectively decode said input signals; and wherein said memory system also includes, a control means for generating a control signal that is in one state during only a small fraction of said read cycle and is otherwise in an opposite state; and an enabling means, coupled between said control means and said logic gates, for reducing power dissipating in said logic gates by decoupling said bus from said gates whenever said control signal is in said opposite state.
Claim 7
Dependent Claim
145 words
A memory system having a storage means which receives an address during a read cycle and which reads data bits and check bits at said address, and a plurality of logic gates which are coupled in parallel which correct errors in said data bits; wherein: each logic gate generates a respective one of said minterms by passing a constant power dissipating current from a common bus to selectively decode said input signals; and wherein said memory system also includes, a control means for generating a control signal that is in one state during only a small fraction of said read cycle and is otherwise in an opposite state; and an enabling means, coupled between said control means and said logic gates, for reducing power dissipating in said logic gates by decoupling said bus from said gates whenever said control signal is in said opposite state.
Claim 8
Dependent Claim
58 words
A memory system according to claim 5 and further including a means for forming new check bits from said data bits which are read from said storage means, and wherein said control means forces said control signal into said opposite state throughout said read cycle when said new check bits are the same as said read check bits.
Claim 9
Dependent Claim
41 words
A memory system according to claim 5 wherein said system also includes a write cycle in which data is written into said storage means, and wherein said control means forces said control signal into said opposite state throughout said write cycle.
Claim 10
Dependent Claim
24 words
A memory system according to claim 5 wherein said system further includes multiple OR gates which are coupled to selectively OR said minterms together.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-11 | 1991-07-13 | 1992-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-11 | 1995-07-13 | 1996-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-11 | 1999-07-13 | 2000-01-12 | $7700.00 | Window Closed / Lapsed |