US3753244A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Yield enhancement redundancy technique
Assignee: International Business Machines Corp
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Filing: 1971-08-18
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Granted: 1973-08-14
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Expires: 1991-08-18
Abstract
Abstract A memory storage system utilizing a plurality of storage devices, each of which contains redundancy and each of which is functionally organized on e.g. a single semiconductor chip with its own decoders. This redundancy in each device is provided by placing an extra line of cells on the chip together with a defective address store and a comparator circuit for disabling a defective line of cells and replacing it with the extra line of cells.
Inventors
- 👤 J Sumilas
- 👤 N Vogl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:22
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/781
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
154 words
A memory storage system comprising a main memory means for storing data in storage cells wherein at least one of said storage cells is a defective cell, a decoder circuit coupled to said main memory means, comparator means, memory address register means for applying first addressing signals to said decoder circuit and to said comparator means, read only memory means for applying second addressing signals, indicative of the location of said defective cell in said main memory, to said comparator means, and alternate data storage means, said comparator means responsive to said first addressing signals and second addressing signals for applying a pulse to said decoder circuit and to said alternate data storage means when said first addressing signals and second addressing signals match, said decoder circuit containing inhibiting means controlled by said pulse to prevent said circuit from producing an addressing output to said storage cells when said first and second signals match.
Claim 2
Dependent Claim
154 words
A memory storage system comprising a main memory means for storing data in storage cells wherein at least one of said storage cells is a defective cell, a decoder circuit coupled to said main memory means, comparator means, memory address register means for applying first addressing signals to said decoder circuit and to said comparator means, read only memory means for applying second addressing signals, indicative of the location of said defective cell in said main memory, to said comparator means, and alternate data storage means, said comparator means responsive to said first addressing signals and second addressing signals for applying a pulse to said decoder circuit and to said alternate data storage means when said first addressing signals and second addressing signals match, said decoder circuit containing inhibiting means controlled by said pulse to prevent said circuit from producing an addressing output to said storage cells when said first and second signals match.
Claim 3
Dependent Claim
31 words
The memory storage system of claim 1 wherein said main memory means comprises a plurality of semiconductor integrated circuit chips, each of said chips having therein said alternate data storage means.
Claim 4
Dependent Claim
40 words
The memory storage system of claim 2 wherein said semiconductor circuit chip further has formed therein said decoder circuit, a set of bit decode circuits coupled to said main memory means, said read only memory means, and said comparator means.
Claim 5
Dependent Claim
60 words
The memory system of claim 1 wherein said comparator means responsive to said first address signals and said second addressing signals comprises a series of exclusive OR circuits, each of said exclusive OR circuits having an input coupled to the address register means an input coupled to the read only memory means, and an output coupled to said decoder circuit.
Claim 6
Dependent Claim
16 words
The memory system of claim 3 wherein said decoder circuit comprises a series of NOR circuits.
Claim 7
Dependent Claim
51 words
The memory system of claim 1 wherein said read only memory means contains an address store of n+1 binary bits where n is the number of binary bits in the first address signal of the memory address register, the extra binary bit being used to disable the alternate data storage means.
Claim 8
Dependent Claim
45 words
The memory system of claim 6 wherein said read only memory means is coupled to said comparator means and to a power source and includes a plurality of fusable means therein which can be permanently blown by said power soUrce to indicate a defective address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-13 | 1977-02-12 | 1977-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-13 | 1981-02-12 | 1981-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-13 | 1985-02-12 | 1985-08-14 | $7700.00 | Window Closed / Lapsed |