US4770640A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrical interconnection device for integrated circuits
Assignee: Individual
•
Filing: 1983-06-24
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Granted: 1988-09-13
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Expires: 2003-06-24
Abstract
Abstract An electrical interconnection device provides electrical connection between any two or more microelectronic layers in a multilayer microelectronic device, or between the layers and an external electrical device. The electrical interconnection device is a monolithic integrated circuit with a pattern of conductive paths fabricated on its surface, and is placed directly against the side edges of a multilayer microelectronic device such that the paths on the electrical interconnection device contact associated conductive pathways exposed at the side edges of the layers of the microelectronic structure.
Inventors
- 👤 Howard F. Walter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:25
CPC Classifications
H; H10; H10W; H10W90/00; H01; H01R; H01R12/00; H01R12/50; H01R12/51; H01R12/52; H10W70/00; H10W70/60; H10W70/611; H10W72/00; H10W72/834; H10W90/20; H10W90/26
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
148 words
A multilayer integrated circuit assembly comprising: a plurality of first integrated circuits, said circuits comprising generally planar interconnected arrays of active and passive barrier layer electrical circuit elements deposited on a single semiconductor substrate by a continuous series of compatible processes and capable of performing at least one complete electronic circuit function, said planar arrays arranged as layers in a layered stack, said layers each including at least one conductive path on a surface of each of said layers, said paths terminating in electrical contact points at side edges of said layers; a second substantially planar integrated circuit having opposed surfaces, a first of said opposed surfaces including a conductive path on a first portion thereof, said first surface portion disposed against said side edges of said layers, said conductive path on said first surface portion in electrical contact with at least one of said electrical contact points.
Claim 2
Dependent Claim
148 words
A multilayer integrated circuit assembly comprising: a plurality of first integrated circuits, said circuits comprising generally planar interconnected arrays of active and passive barrier layer electrical circuit elements deposited on a single semiconductor substrate by a continuous series of compatible processes and capable of performing at least one complete electronic circuit function, said planar arrays arranged as layers in a layered stack, said layers each including at least one conductive path on a surface of each of said layers, said paths terminating in electrical contact points at side edges of said layers; a second substantially planar integrated circuit having opposed surfaces, a first of said opposed surfaces including a conductive path on a first portion thereof, said first surface portion disposed against said side edges of said layers, said conductive path on said first surface portion in electrical contact with at least one of said electrical contact points.
Claim 3
Dependent Claim
40 words
The device of claim 1 wherein one of said layers includes a plurality of conductive paths and corresponding contact points and said conductive path on said first surface portion contacts said plurality of electrical contact points located on said layer.
Claim 4
Dependent Claim
28 words
The device of claim 1 wherein said conductive path on said first surface portion contacts a plurality of electrical contact points located on a plurality of said layers.
Claim 5
Dependent Claim
39 words
The device of claim 1 wherein said first surface portion includes a predetermined pattern comprised of a plurality of conductive paths arranged for electrical contact with selected ones of a plurality of said electrical contact points of said layers.
Claim 6
Dependent Claim
44 words
The device of claim 4 wherein at least one of said conductive paths extends from said first surface portion to a second portion of said first surface, said at least one conductive path terminates in an electrical contact pad on said second surface portion.
Claim 7
Dependent Claim
55 words
The device of claim 4 wherein at least two of said plurality of conductive paths extend from said first surface portion to a second portion of said first surface and terminate in two electrical contact pads on said second surface portion, and wherein said plurality of electrical contact points are located on the same layer.
Claim 8
Dependent Claim
62 words
The device of claim 4 wherein said plurality of conductive paths extend from said first surface portion to a second portion of said first surface and terminate in a respective plurality of electrical contact pads on said second surface portion, and further comprising a microprocessor located on said second portion and electrically connected to selected ones of said plurality of conductive paths.
Claim 9
Dependent Claim
124 words
An electrical circuit assembly comprising: a stack of integrated circuits, said integrated circuits comprising generally planar interconnected arrays of active and passive barrier layer electrical circuit elements deposited in a single semi-conductor substrate by a continuous series of compatible processes including etching and photolithographic processes, said planar arrays including edge portions, said edge portions provided with electrical contact means, said contact means formed by means of said processes and connecting said integrated circuits into a circuit assembly; an electrical circuit interconnecting device comprising a generally planar surface having conductive paths thereon and disposed adjacent said edge portions for selective electrical contact of said conductive paths with said contact means; microprocessor means located on said surface and electrically connected in circuit with said conductive paths.
Claim 10
Dependent Claim
124 words
An electrical circuit assembly comprising: a stack of integrated circuits, said integrated circuits comprising generally planar interconnected arrays of active and passive barrier layer electrical circuit elements deposited in a single semi-conductor substrate by a continuous series of compatible processes including etching and photolithographic processes, said planar arrays including edge portions, said edge portions provided with electrical contact means, said contact means formed by means of said processes and connecting said integrated circuits into a circuit assembly; an electrical circuit interconnecting device comprising a generally planar surface having conductive paths thereon and disposed adjacent said edge portions for selective electrical contact of said conductive paths with said contact means; microprocessor means located on said surface and electrically connected in circuit with said conductive paths.
Claim 11
Dependent Claim
22 words
The device of claim 8 wherein said microprocessor multiplexes and demultiplexes electrical signals between selected ones of said plurality of conductive paths.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-13 | 1992-03-14 | 1992-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-13 | 1996-03-14 | 1996-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-13 | 2000-03-14 | 2000-09-13 | $7700.00 | Window Closed / Lapsed |