Multi-layer dielectric planar structure having an internal conductor pattern characterized with opposite terminations disposed at a common edge surface of the layers

Claim 1

A planar support for attachment to at least one semiconductor device having a plurality of terminals fixed thereon and arranged in a first grid pattern upon one side of the device, comprising (A) a unitized plurality of superposed dielectric planar layers, (B) a conductor pattern comprised of a plurality of conductor leads between at least one original adjacent pair of said layers and extending in a return path to and between a common edge surface of said layers, (a) with said conductor leads substantially coextensive and parallel with the planes of said layers, (b) with said edge surfaces disposed at the ends of the original interfaces of said layers, (c) with the common adjacent terminations of said leads disposed at a first portion of said edge surface in a configuration corresponding to a first grid pattern of predetermined spacing, and (d) with the opposite common terminations of said leads disposed at a second portion of said edge surface in a second grid pattern having spacings substantially larger than said first spacing, (C) a distribution pattern of conductors on said edge surface and comprised of a plurality of leads having one end connected to respective ones of opposite terminations with the opposite ends terminating at dispersed contact points on a third portion of said edge surface with the spacing between said points being substantially greater than the spacing of both said first and second grid patterns, and (D) contact pins extending from said contact points to the opposite edge surface of said layers in projecting relationship therefrom, with said contact pins coextending with and parallel with the planes of said layers and conductor pattern.