Patent US3739462A successfully refreshed from Google Patents.
US3972028A
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Data processing system including a plurality of memory chips each provided with its own address register
Assignee: Olympia Werke AG
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Filing: 1974-12-20
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Granted: 1976-07-27
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Expires: 1994-12-20
Abstract
Abstract In a circuit arrangement composed of a plurality of highly integrated MOS circuit chips, for use in a data processing device, one chip being an arithmetic and control unit and further chips containing memories, each further chip is also provided with an address register capable of storing a selected memory location address and an address selecting the memory of a selected memory chip for read-out and arranged to count through the successive memory location addresses and to change the memory selecting address after the count reaches the last memory location address, such counting being effected by counting pulses.
Inventors
- 👤 Gerald Weber
- 👤 Jurgen Sorgenfrei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:42
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7864; G06F12/0215
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
200 words
In a circuit arrangement composed of a plurality of chips containing highly integrated circuit components for use in a data processing device, one said chip containing components interconnected to form an arithmetic and control unit for performing the arithmetic operations and controlling the operation of said arrangement and at least two others of said chips each constituting a memory chip containing components defining a memory having a plurality of addressable "memory locations, said arrangement also including a plurality of conductors interconnecting said chips and defining a collecting bus, the improvement wherein each said memory chip further includes components interconnected to define an address register having a first group of address bit locations arranged to contain an address word for addressing any selecing memory location of the memory on its respective memory chip, and having a second group of address bit locations arranged to contain a bit sequence for selecting the memory of one of said memory chips for read-out, there being a respective bit sequence corresponding to ach said memory chip, and each said register having a counting pulse input and being arranged to count through successive memory word addresses in response to pulses applied to its counting pulse input.
Claim 2
Dependent Claim
200 words
In a circuit arrangement composed of a plurality of chips containing highly integrated circuit components for use in a data processing device, one said chip containing components interconnected to form an arithmetic and control unit for performing the arithmetic operations and controlling the operation of said arrangement and at least two others of said chips each constituting a memory chip containing components defining a memory having a plurality of addressable "memory locations, said arrangement also including a plurality of conductors interconnecting said chips and defining a collecting bus, the improvement wherein each said memory chip further includes components interconnected to define an address register having a first group of address bit locations arranged to contain an address word for addressing any selecing memory location of the memory on its respective memory chip, and having a second group of address bit locations arranged to contain a bit sequence for selecting the memory of one of said memory chips for read-out, there being a respective bit sequence corresponding to ach said memory chip, and each said register having a counting pulse input and being arranged to count through successive memory word addresses in response to pulses applied to its counting pulse input.
Claim 3
Dependent Claim
92 words
An arrangement as defined in claim 1 wherein each said register has both of its groups of bit locations inerconnected to have the content of its first group of bit locations count through the addresses of all memory locations of its respective memory and to increase the binary value of the bit sequence contained in its second group of bit locations after there has appeared at its first group of bit locations an address word constituted by the highest binary value which said first group of bit locations is capable of containing.
Claim 4
Dependent Claim
13 words
An arrangement as defined in claim 1 wherein said components are MOS components.
Claim 5
Dependent Claim
38 words
An arrangement as defined in claim 1 further comprising means connected between said arithmetic and control unit and each said register for supplying signals for setting a selected bit value into each bit location of each said register.
Claim 6
Dependent Claim
25 words
An arrangement as defind in claim 4 wherein each said memory is a read-only memory containing successive microprogram instruction words in sequentially addressable memory locations.
Claim 7
Dependent Claim
59 words
An arrangement as defined in claim 5 wherein at least one said memory chip further contains a plurality of further address registers for containing return addresses, and connected to said first recited register of said one memory chip for transferring the content of each said further register to said first-recited register upon completion of processing of a respective subprogram.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-27 | 1980-01-26 | 1980-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-27 | 1984-01-26 | 1984-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-27 | 1988-01-26 | 1988-07-27 | $7700.00 | Window Closed / Lapsed |