Patent DE567506C successfully refreshed from Google Patents.
US4933835A
Expired / Lapsed
US
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Apparatus for maintaining consistency of a cache memory with a primary memory
Assignee: Intergraph Corp
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Filing: 1989-01-19
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Granted: 1990-06-12
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Expires: 2009-01-19
Abstract
Abstract A microprocessor system is disclosed having a high speed system bus for coupling system elements, and having a dual bus microprocessor with separate ultra-high speed instruction and data cache-MMU interfaces coupled to independently operable instruction and data cache-MMU, respectively. A main memory is coupled to the system bus for selectively storing and outputting digital information. The instruction and data cache-MMU's are coupled to the main memory via the system bus for independently storing and outputting digital information to respective mapped addressable very high speed cache memory. The microprocessor is coupled via separate and independent very high speed instruction and data buses to each of the instruction cache-MMU and data cache-MMU, respectively, for processing data received from the data cache-MMU responsive to instructions received from the instruction cache-MMU. The instruction bus and data bus are exclusive and independent of one another, and allow for simultaneous very high-speed transfer. The data cache-MMU and instruction cache-MMU each have separate dedicated system bus interfaces for coupling to the main memory and to other peripheral devices which are coupled to the system bus. Numerous other system elements can also be coupled to the system bus, including an interrupt controller, an I/O processor, a bus arbiter, an array processor, and other peripheral controller devices.
Inventors
- 👤 Howard G. Sachs
- 👤 James Y. Cho
- 👤 Walter H. Hollingsworth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:55
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
172 words
A computer system comprising: primary memory means for storing data at storage locations therein; system bus means, coupled to the primary memory, for communicating data with the primary memory means; a first data processing element, coupled to the system bus means, for processing data from the primary memory means; a second data processing element for processing data from the primary memory means; cache memory means for storing data from the primary memory means, wherein data from the primary memory processed by the first and second data processing elements may be stored in the cache memory; and cache controller means, coupled to the system bus means, to the second data processing element, and to the cache memory means, for selectively communicating data between the primary memory means and the cache memory means and for communicating data between the cache memory means and the second data processing element, the cache controller means including primary memory access detecting means for detecting when the primary memory means is being accessed by the first data processing element.
Claim 2
Dependent Claim
172 words
A computer system comprising: primary memory means for storing data at storage locations therein; system bus means, coupled to the primary memory, for communicating data with the primary memory means; a first data processing element, coupled to the system bus means, for processing data from the primary memory means; a second data processing element for processing data from the primary memory means; cache memory means for storing data from the primary memory means, wherein data from the primary memory processed by the first and second data processing elements may be stored in the cache memory; and cache controller means, coupled to the system bus means, to the second data processing element, and to the cache memory means, for selectively communicating data between the primary memory means and the cache memory means and for communicating data between the cache memory means and the second data processing element, the cache controller means including primary memory access detecting means for detecting when the primary memory means is being accessed by the first data processing element.
Claim 3
Dependent Claim
27 words
The computer system according to claim 1 wherein the system bus means further comprises access indicating means for indicating when the primary memory means is being accessed.
Claim 4
Dependent Claim
45 words
The computer system according to claim 2 wherein the cache controller means further comprises cache inquiry means, responsive to the access indicating means, for determining whether a storage location being accessed in the primary memory means corresponds to data stored in the cache memory means.
Claim 5
Dependent Claim
50 words
The computer system according to claim 3 wherein the primary memory means further comprises access control means for selectively allowing and inhibiting access to the primary memory means when the storage location to be accessed in the primary memory means may correspond to data stored in the cache memory means.
Claim 6
Dependent Claim
66 words
The computer system according to claim 4 wherein the cache controller means further comprises inquiry indicating means, coupled to the cache inquiry means and to the system bus means, for providing a first cache inquiry signal to the system bus means when the cache inquiry means is determining whether the primary memory storage location to be accessed corresponds to data stored in the cache memory means.
Claim 7
Dependent Claim
27 words
The computer system according to claim 5 wherein the access control means inhibits access to the primary memory means in response to the first cache inquiry signal.
Claim 8
Dependent Claim
41 words
The computer system according to claim 6 wherein the inquiry indicating means provides a second cache inquiry signal to the system bus when the cache inquiry means has determined whether the data to be accessed is stored in the cache memory.
Claim 9
Dependent Claim
26 words
The computer system according to claim 7 wherein the access control means allows access to the primary memory in response to the second cache inquiry signal.
Claim 10
Dependent Claim
39 words
The computer system according to claim 3 wherein the access indicating means further comprises read indicating means for providing a read indicating signal when data is to be retrieved from a selected storage location in the primary memory means.
Claim 11
Dependent Claim
50 words
The computer system according to claim 9 wherein, when the selected primary memory storage location corresponds to data stored in the cache memory, the cache controller means couples the cache data corresponding to the selected primary memory storage location to the system bus in response to the read indicating signal.
Claim 12
Dependent Claim
38 words
The computer system according to claim 10 wherein the cache controller means couples the cache data to the system bus only when the cache data has been modified since the cache data was stored in the cache memory.
Claim 13
Dependent Claim
32 words
The computer system according to claim 10 wherein the cache controller means provides a first ready signal to the system bus means when the cache data is coupled to the system bus.
Claim 14
Dependent Claim
64 words
The computer system according to claim 12 wherein the cache controller means further comprises inquiry indicating means, coupled to the cache inquiry means and to the system bus means, for providing a first cache inquiry signal to the system bus means when the cache inquiry means is determining whether the selected primary memory storage location corresponds to data stored in the cache memory means.
Claim 15
Dependent Claim
44 words
The computer system according to claim 13 wherein the inquiry indicating means provides a second cache inquiry signal to the system bus when the cache inquiry means has determined whether the selected primary memory storage location corresponds to data stored in the cache memory.
Claim 16
Dependent Claim
38 words
The computer system according to claim 14 wherein the primary memory means couples data from the selected storage location to the system bus when the second cache inquiry signal is provided and the first ready signal is absent.
Claim 17
Dependent Claim
35 words
The computer system according to claim 15 wherein the primary memory means provides a second ready signal to the system bus when the data from the selected storage location is coupled to the system bus.
Claim 18
Dependent Claim
38 words
The computer system according to claim 15 wherein the access indicating means further comprises data type means for indicating whether the selected primary memory storage location corresponds to data which may be stored in the cache memory means.
Claim 19
Dependent Claim
41 words
The computer system according to claim 17 wherein the cache inquiry means initiates a cache inquiry when the data type means indicates that the selected primary memory storage location corresponds to data which may be stored in the cache memory means.
Claim 20
Dependent Claim
38 words
The computer system according to claim 18 wherein the cache inquiry means does not initiate a cache inquiry when the data type means indicates that the data to be accessed is not store in the cache memory means.
Claim 21
Dependent Claim
35 words
The computer system according to claim 19 wherein the second cache inquiry signal is provided when the data type means indicates that the data to be accessed is not stored in the cache memory means.
Claim 22
Dependent Claim
32 words
The computer system according to claim 12 wherein the cache controller means includes means for invalidating the data stored in the cache memory which corresponds to the selected primary memory storage location.
Claim 23
Dependent Claim
35 words
The computer system according to claim 3 wherein the access indicating means further comprises write indicating means for indicating when data is to be transferred to a selected storage location in the primary memory means.
Claim 24
Dependent Claim
48 words
The computer system according to claim 21 wherein the cache controller means includes means for updating the cache memory with the data to be transferred to the selected primary memory storage location when the selected primary memory storage location corresponds to data stored in the cache memory means.
References Cited (Backward Citations)
US3693765A
Cited
US3761881A
Cited
US4439824A
Cited
US3764996A
Cited
US3723976A
Cited
US3902164A
Cited
GB1444228A
Cited
US3898624A
Cited
US3956737A
Cited
US3896419A
Cited
US4057848A
Cited
US4037209A
Cited
US4068303A
Cited
US4173783A
Cited
US4077059A
Cited
US4151593A
Cited
US4144563A
Cited
US4179734A
Cited
US4195352A
Cited
US4161036A
Cited
US4228497A
Cited
US4229789A
Cited
US4161024A
Cited
US4189767A
Cited
US4500962A
Cited
US4215402A
Cited
US4257097A
Cited
US4314331A
Cited
US4325120A
Cited
US4295193A
Cited
US4310880A
Cited
US4443848A
Cited
US4354225A
Cited
US4405980A
Cited
US4502110A
Cited
US4727484A
Cited
US4392200A
Cited
US4415969A
Cited
US4360869A
Cited
US4371928A
Cited
US4348724A
Cited
US4398243A
Cited
US4493020A
Cited
US4381541A
Cited
US4386402A
Cited
US4481573A
Cited
US4407015A
Cited
US4482952A
Cited
US4378591A
Cited
US4392201A
Cited
US4400774A
Cited
US4407016A
Cited
US4513369A
Cited
US4507728A
Cited
US4464712A
Cited
JPS5858666A
Cited
US4563737A
Cited
US4442487A
Cited
US4498135A
Cited
US4604688A
Cited
US4654819A
Cited
US4581702A
Cited
US4635194A
Cited
JPS6041146A
Cited
US4731739A
Cited
US4682281A
Cited
JPS60120450A
Cited
US4680700A
Cited
JPS60144847A
Cited
US4669043A
Cited
US4701844A
Cited
US4680702A
Cited
US4620275A
Cited
US4685082A
Cited
US4740969A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-11 | 1993-12-11 | 1994-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-11 | 1997-12-11 | 1998-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-11 | 2001-12-11 | 2002-06-12 | $7700.00 | Window Closed / Lapsed |