US4407015A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple event driven micro-sequencer
Assignee: Unisys Corp
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Filing: 1980-11-26
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Granted: 1983-09-27
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Expires: 2000-11-26
Abstract
Abstract A micro-sequencer allowing multiple decisions to be made in one instant of time is disclosed. A multiplexor array is employed to generate a multiple output condition code from inputted test conditions. The generated condition code is concatenated to a base pointer field of the currently executing microinstruction, and the result is used to address a next state table. The output of the next state table is the address of the microinstruction to be executed next if the then currently executing microinstruction specifies a jump operation.
Inventors
- 👤 Daniel P. Ziobro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:27
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/261; G06F9/262; G06F9/264
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
116 words
A multiple event driven micro-sequencer for use in a microprogram controlled system, said microprogram controlled system including an addressable storage for storing microinstructions, said microprogram controlled system capable of activating selected control signals in response to executing said microintructions, said multiple event driven micro-sequencer comprising: register-counter means, coupled to said addressable storage, said register-counter means for storing the address of the addressable storage location to be accessed; means for generating a condition code, said condition code generating means responsive to a plurality of inputted test conditions; and next state means, responsive to said generated condition code and said microprogram controlled system, said next state means for providing said register-counter means with an entire next state address.
Claim 2
Dependent Claim
116 words
A multiple event driven micro-sequencer for use in a microprogram controlled system, said microprogram controlled system including an addressable storage for storing microinstructions, said microprogram controlled system capable of activating selected control signals in response to executing said microintructions, said multiple event driven micro-sequencer comprising: register-counter means, coupled to said addressable storage, said register-counter means for storing the address of the addressable storage location to be accessed; means for generating a condition code, said condition code generating means responsive to a plurality of inputted test conditions; and next state means, responsive to said generated condition code and said microprogram controlled system, said next state means for providing said register-counter means with an entire next state address.
Claim 3
Dependent Claim
41 words
The multiple event driven micro-sequencer in accordance with claim 1 wherein said next state means includes an addressable next state memory, said addressable next state memory responsive to an address formed by concatenating said generated condition code with a base address.
Claim 4
Dependent Claim
31 words
The multiple event driven micro-sequencer in accordance with claim 2 wherein said base address includes a field of information from the last one of said microinstructions read from said addressable storage.
Claim 5
Dependent Claim
63 words
The multiple event driven micro-sequencer in accordance with claim 2 or 3 wherein said concatenated address includes a number of high order bit positions and a number of low order bit positions, said concatenated address formed using said base address as said number of the high order bit positions and said generated condition code as said number of the low order bit positions.
Claim 6
Dependent Claim
49 words
The multiple event driven micro-sequencer in accordance with claim 2 wherein said register-counter means includes next state storage means, responsive to a jump control signal from said microprogram controlled system, said next state storage means for storing the entire next state address provided by said addressable next state memory.
Claim 7
Dependent Claim
44 words
The multiple event driven micro-sequencer in accordance with claim 5 wherein said register-counter means further includes incrementing means, responsive to a step control signal from said microprogram controlled system, said incrementing means for incrementing the contents of said register-counter means by a fixed increment.
Claim 8
Dependent Claim
25 words
The multiple event driven micro-sequencer in accordance with claim 1 or 2 wherein said generated condition code is at least two bit positions in length.
Claim 9
Dependent Claim
46 words
The multiple event driven micro-sequencer in accordance with claim 1 or 2 wherein said condition code generating means includes a plurality of multiplexor circuits, each one of said multiplexor circuits including inputs for accepting a subset of said plurality of inputted test conditions and an output.
Claim 10
Dependent Claim
51 words
The multi event driven micro-sequencer in accordance with claim 8 wherein said generated condition code is formed by combining the output of each one of said plurality of multiplexor circuits, the output of each one of said multiplexor circuits responsive to a condition code multiplex address from said microprogram controlled system.
Claim 11
Dependent Claim
34 words
The multiple event driven micro-sequencer in accordance with claim 2 wherein said addressable next state memory, in response to an access to said concatenated address, produces at its input said entire next state address.
Claim 12
Dependent Claim
82 words
The multiple event driven micro-sequencer in accordance with claim 1 wherein said next state means includes: a plurality of addressable next state memories, each of said plurality of addressable next state memories responsive to a common base address; and a multiplexor circuit having inputs for simultaneously receiving the outputs from each of said plurality of addressable next state memories, said multiplexor circuit responsive to said generated condition code to select the output of one of said plurality of addressable next state memories.
References Cited (Backward Citations)
US3939455A
Cited
US3798614A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-26 | 1987-03-28 | 1987-09-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-26 | 1991-03-28 | 1991-09-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-26 | 1995-03-28 | 1995-09-27 | $7700.00 | Window Closed / Lapsed |