US4400774A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cache addressing arrangement in a computer system
Assignee: AT&T Inc
•
Filing: 1981-02-02
•
Granted: 1983-08-23
•
Expires: 2001-02-02
Abstract
Abstract In a computer system having a cache memory and using virtual addressing, effectiveness of the cache is improved by storing a subset of the least significant real address bits obtained by translation of a previous virtual address and by using this subset in subsequent cache addressing operations. The system functions in the following manner. In order to access a memory location in either the main memory or cache memory, a processor generates and transmits virtual address bits to the memories. The virtual address bits comprise segment, page and word address bits. The word address bits do not have to be translated, but an address translation buffer (ATB) translates the segment and page address into real address bits. A subset of the least significant bits of the latter word address bits represent the address needed for accessing the cache. In order to increase cache memory performance, the cache memory comprises a cache address unit which stores the subset of the real address bits from the ATB. These stored address bits are used in subsequent operations along with the word address bits for accessing the cache memory until the stored address bits no longer equal the current subset of least significant real address bits transmitted from the ATB. When the stored address bits no longer equal the current subset, the cache address unit then stores the current subset; and the cache memory is reaccessed utilizing the word address bits and current subset.
Inventors
- 👤 Wing N. Toy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:43
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
237 words
A computer system comprising: a processor for generating and transmitting read control signals and virtual address signals including word address signals; cache memory means having a plurality of word locations; address translation means responsive to certain of said virtual address signals for generating present cache address signals and other address signals; memory access control means comprising address storage means for storing previous cache address signals and cache control means responsive to said read control signals to transmit a first cache control signal and the stored previous cache address signals to said cache memory; said cache memory means being responsive to said first cache control signal, said stored address signals, and said word address signals to read a first one of said plurality of word locations for transmitting the contents of said first one of said plurality of word locations to said processor; said memory access control means further comprising comparator means for comparing said stored address signals and said present cache address signals to generate a first compare signal if said stored address signals equal said present cache address signals and to generate a second compare signal if said stored address signals are not equal to said present cache address signals; said cache control means being responsive to said first compare signal to generate and to transmit a completion signal to said processor and responsive to said second compare signal to generate a second cache control signal.
Claim 2
Dependent Claim
237 words
A computer system comprising: a processor for generating and transmitting read control signals and virtual address signals including word address signals; cache memory means having a plurality of word locations; address translation means responsive to certain of said virtual address signals for generating present cache address signals and other address signals; memory access control means comprising address storage means for storing previous cache address signals and cache control means responsive to said read control signals to transmit a first cache control signal and the stored previous cache address signals to said cache memory; said cache memory means being responsive to said first cache control signal, said stored address signals, and said word address signals to read a first one of said plurality of word locations for transmitting the contents of said first one of said plurality of word locations to said processor; said memory access control means further comprising comparator means for comparing said stored address signals and said present cache address signals to generate a first compare signal if said stored address signals equal said present cache address signals and to generate a second compare signal if said stored address signals are not equal to said present cache address signals; said cache control means being responsive to said first compare signal to generate and to transmit a completion signal to said processor and responsive to said second compare signal to generate a second cache control signal.
Claim 3
Dependent Claim
102 words
A computer system in accordance with claim 1 wherein said address storage means comprises means responsive to said second cache control signal to store said present cache address signals as a new set of previous cache address signals and to transmit said present cache address signals to said cache memory; said cache memory means is further responsive to said second cache control signal, said transmitted present cache address signals, and said word address signals to read a second one of said plurality of word locations for transmitting the contents of said second one of said plurality of word locations to said processor.
Claim 4
Dependent Claim
202 words
A computer system in accordance with claim 2 wherein said read control signals comprise an instruction signal and a data signal; said stored previous cache address signals comprise instruction address signals and data address signals; said address storage means further comprises a first register means for storing said instruction address signals, a second register means for storing said data address signals, and selector means responsive to said instruction signal for transmitting said stored instruction address signals to said cache memory means; said cache memory further being responsive to said first cache control signal, the transmitted instruction address signals, and said word address signals to read a third one of said plurality of word locations for transmitting the contents of said third one of said plurality of word locations to said processor; said selector means further responsive to said data signal for transmitting said stored data address signals to said cache memory; and said cache memory further being responsive to said first cache control signal, the transmitted data address signals, and said word address signals to read a fourth one of said plurality of word locations for transmitting the contents of said fourth one of said plurality of word locations to said processor.
Claim 5
Dependent Claim
72 words
A computer system in accordance with claim 3 wherein said first register means is responsive to said second cache control signal and said instruction signal to store said present cache address signals as a new set of instruction address signals; and said second register means is responsive to said second cache control signal and said data signal to store said present cache address signals as a new set of data address signals.
Claim 6
Dependent Claim
288 words
A computer system comprising a processor for generating and transmitting a read control signal and virtual address signals including word address signals; address translation means responsive to certain of said virtual address signals for generating present cache address signals and other address signals; cache memory means comprising tag memory means for storing tag data words, and data memory means for storing information data words; memory access control means comprising address storage means for storing previous cache address signals and cache control means responsive to said read control signal to transmit a first cache control signal and the stored previous cache address signals to said cache memory; said memory access control means further comprising comparator means for comparing said stored address signals and said present cache address signals to generate a first comparison signal if said stored address signals equal said present cache address signals and to generate a second compare signal if said stored address signals are not equal to said present cache address signals; said tag memory and said data memory being responsive to said first cache control signal, said stored address signals, and said word address signals to read a tag data word and an information data word, respectively; cache address comparison means responsive to said other address signals and said tag data word to generate and to transmit to said cache control means a third compare signal if said other address signals equal said tag data word and to generate a fourth compare signal if said other address signals do not equal said tag data word; and said cache control means is responsive to concurrent generation of said first and said third compare signals to generate and to transmit said completion signal to said processor.
Claim 7
Dependent Claim
288 words
A computer system comprising a processor for generating and transmitting a read control signal and virtual address signals including word address signals; address translation means responsive to certain of said virtual address signals for generating present cache address signals and other address signals; cache memory means comprising tag memory means for storing tag data words, and data memory means for storing information data words; memory access control means comprising address storage means for storing previous cache address signals and cache control means responsive to said read control signal to transmit a first cache control signal and the stored previous cache address signals to said cache memory; said memory access control means further comprising comparator means for comparing said stored address signals and said present cache address signals to generate a first comparison signal if said stored address signals equal said present cache address signals and to generate a second compare signal if said stored address signals are not equal to said present cache address signals; said tag memory and said data memory being responsive to said first cache control signal, said stored address signals, and said word address signals to read a tag data word and an information data word, respectively; cache address comparison means responsive to said other address signals and said tag data word to generate and to transmit to said cache control means a third compare signal if said other address signals equal said tag data word and to generate a fourth compare signal if said other address signals do not equal said tag data word; and said cache control means is responsive to concurrent generation of said first and said third compare signals to generate and to transmit said completion signal to said processor.
Claim 8
Dependent Claim
38 words
A computer system in accordance with claim 5 wherein said cache control means is responsive to said second compare signal to inhibit the transmission of said completion signal to said processor in response to said third compare signal.
Claim 9
Dependent Claim
40 words
A computer system in accordance with claim 6 characterized in that said cache control means is responsive to said fourth compare signal to inhibit the transmission of said completion signal to said processor in response to said first compare signal.
References Cited (Backward Citations)
US3693165A
Cited
US3786427A
Cited
US3761881A
Cited
US3723976A
Cited
US3825904A
Cited
US3979726A
Cited
US4084230A
Cited
US4128875A
Cited
US4096573A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-22 | 1987-02-21 | 1987-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-22 | 1991-02-21 | 1991-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-22 | 1995-02-21 | 1995-08-23 | $7700.00 | Window Closed / Lapsed |