US4398243A
Expired / Lapsed
US
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Data processing system having a unique instruction processor system
Assignee: EMC Corp
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Filing: 1980-04-25
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Granted: 1983-08-09
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Expires: 2000-04-25
Abstract
Abstract A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different level of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.
Inventors
- 👤 Kenneth D. Holberger
- 👤 James E. Veres
- 👤 Michael L. Ziegler
- 👤 Carl Henry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 00:40
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/14; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292; G06F12/08; G06F12/0802; G06F12/10; G06F12/1009; G06F12/14; G06F9/22; G06F9/26; G06F11/1008; G06F11/1048; G06F11/106; G06F12/06; G06F12/0615; G06F12/0623
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
311 words
In a data processing system, an instruction processor means for decoding a plurality of first instructions forming a first designated basic instruction set the addresses of which have a first selected number of bits and a plurality of second instructions forming a second designated extended instruction set the addresses of which have a second selected number of bits different from said first selected number, each of said first or second instructions including at least an operating code portion which includes a selected bit code combination which identifies whether said instruction is from said basic instruction set or from said extended instruction set and some of said first and second instructions further including at least one displacement portion, said instruction processor means comprising instruction decode register means having at least two register regions, a first of said regions designated to temporarily store said operating code portion of an instruction and said at least one other region designated to temporarily store a displacement portion; means for supplying an incoming instruction of said basic instruction set or said extended instruction set; instruction decode shifter means connected to said instruction supplying means and responsive to said incoming instruction for entering said incoming instruction into said instruction decode register means so that said first designated region temporarily stores the operating code portion thereof and said at least one other designated region, if required, temporarily stores a displacement portion thereof; means responsive to the selected bit code combination of each incoming instruction for identifying whether said instruction is from basic instruction set or from said extended instruction set; and means for decoding the operating code portion of said identified instruction supplied thereto from said instruction decode register means to produce a plurality of operating code descriptors associated with said decoded instruction and for producing a starting address of one or more microinstructions associated with said decoded instruction.
Claim 2
Dependent Claim
311 words
In a data processing system, an instruction processor means for decoding a plurality of first instructions forming a first designated basic instruction set the addresses of which have a first selected number of bits and a plurality of second instructions forming a second designated extended instruction set the addresses of which have a second selected number of bits different from said first selected number, each of said first or second instructions including at least an operating code portion which includes a selected bit code combination which identifies whether said instruction is from said basic instruction set or from said extended instruction set and some of said first and second instructions further including at least one displacement portion, said instruction processor means comprising instruction decode register means having at least two register regions, a first of said regions designated to temporarily store said operating code portion of an instruction and said at least one other region designated to temporarily store a displacement portion; means for supplying an incoming instruction of said basic instruction set or said extended instruction set; instruction decode shifter means connected to said instruction supplying means and responsive to said incoming instruction for entering said incoming instruction into said instruction decode register means so that said first designated region temporarily stores the operating code portion thereof and said at least one other designated region, if required, temporarily stores a displacement portion thereof; means responsive to the selected bit code combination of each incoming instruction for identifying whether said instruction is from basic instruction set or from said extended instruction set; and means for decoding the operating code portion of said identified instruction supplied thereto from said instruction decode register means to produce a plurality of operating code descriptors associated with said decoded instruction and for producing a starting address of one or more microinstructions associated with said decoded instruction.
Claim 3
Dependent Claim
92 words
In a data processing system in accordance with claim 1 wherein said instruction processor means further includes displacement handling means connected to said instruction decode register means and to said decoding means and responsive to a displacement portion of an instruction, if included therein, from said instruction decode register means and to selected ones of said operating code descriptors from said decoding means for providing a displacement word having a predetermied number of bits, the displacement portions of which are arranged in a selected format for use by said data processing system.
Claim 4
Dependent Claim
56 words
In a data processing system in accordance with claim 2 wherein said displacement handling means includes sign extend logic means responsive to selected ones of said operating code descriptors and to a displacement portion of an instruction, if included therein, for extending the displacement portion by sign extended data, if necessary, to produce said displacement word.
Claim 5
Dependent Claim
59 words
In a data processing system in accordance with claim 2 wherein said displacement handling means includes zero extend logic means responsive to selected ones of said operating code descriptors and to a displacement portion of an instruction, if included therein, for extending the displacement portion by a selected number of zero bits, if necessary, to produce said displacement word.
Claim 6
Dependent Claim
39 words
In a data processing system in accordance with claim 2 wherein said displacement handling means further includes means responsive to said displacement word for supplying said displacement word to said system for use in an arithmetic or logical operation.
Claim 7
Dependent Claim
38 words
In a data processing system in accordance with claim 2 wherein said displacement handling means further includes means responsive to said displacement word for supplying a logical address word to provide a memory reference address to said system.
Claim 8
Dependent Claim
49 words
In a data processing system in accordance with claim 2 wherein said instruction processor means decodes said incoming instruction to provide said starting address and said displacement word, if required, while the one or more microinstructions associated with the starting address of the preceding decoded instruction are being executed.
Claim 9
Dependent Claim
86 words
In a data processing system in accordance with claim 1 said instruction processor means further including instruction cache storage means for storing a plurality of instructions only; means for identifying whether a requested instruction is stored in said instruction cache storage means; said instruction cache storage means being responsive to the address of said requested instruction stored therein when said identifying means indicates that said requested instruction is stored in said instruction cache storage means for supplying said requested instruction to said instruction decode shifter means.
Claim 10
Dependent Claim
56 words
In a data processing system in accordance with claim 8 wherein said data processing system includes a main memory means, said instruction processor means further including means for accessing said requested instruction from said main memory storage means when said identifying means indicates that said requested instruction is not stored in said instruction cache storage means.
Claim 11
Dependent Claim
43 words
In a data processing system in accordance with claim 9, said instruction processor means further including means for providing a direct transmission path to said instruction decode shifter means for a requested instruction which has been accessed from said main memory storage means.
Claim 12
Dependent Claim
65 words
In a data processing system in accordance with claim 1 wherein said instruction decoding means is an array of programmable read-only-memories connected to said instruction decode register means and responsive to the operating code portions of an instruction supplied from said first region thereof for decoding said operating code portion to produce the starting microaddress of one or more microinstructions associated with said decoded instruction.
Claim 13
Dependent Claim
41 words
A data processing system in accordance with claim 11 wherein said array of programmable read-only-memories includes first programmable read-only-memory means for decoding instructions of said basic instruction set and second programmable read-only-memory means for decoding instructions of said extended instruction set.
Claim 14
Dependent Claim
60 words
A data processing system in accordance with claim 12 said instruction processor means further including means responsive to said selected bit code combination for enabling a selected one of said first or second programmable read-only-memory means to decode said instruction depending on whether the instruction to be decoded is from said basic instruction set or from said extended instruction set.
Claim 15
Dependent Claim
41 words
A data processing system in accordance with claim 13 wherein said selected bit code combination comprises a 1 in bit .0. and 1001 in bits 12-15 of said instruction for identifying a first group of instructions from said extended instruction set.
Claim 16
Dependent Claim
41 words
A data processing system in accordance with claim 13 wherein said selected bit code combination comprises a 1 in bit .0. and 011000 in bits 10-15 of said instruction for identifying a first group of instructions from said extended instruction set.
Claim 17
Dependent Claim
46 words
A data processing system in accordance with claim 13 wherein said selected bit code combination comprises a 1 in bit .0., a 0 in bit 5 and 111000 in bits 10-15 of said instruction for identifying a third group of instructions from said extended instruction set.
Claim 18
Dependent Claim
37 words
A data processing system in accordance with claim 13 wherein said selected bit code combination comprises a 0 in bit .0. and 1000 in bits 12-15 of said instruction for identifying instructions from said basic instruction set.
References Cited (Backward Citations)
US3422401A
Cited
US3710324A
Cited
US3991404A
Cited
US4038533A
Cited
US4099229A
Cited
US4155119A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-08 | 1987-02-07 | 1987-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-08 | 1991-02-07 | 1991-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-08 | 1995-02-07 | 1995-08-09 | $7700.00 | Window Closed / Lapsed |