US3764996A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Storage control and address translation
Assignee: International Business Machines Corp
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Filing: 1971-12-23
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Granted: 1973-10-09
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Expires: 1991-12-23
Abstract
Abstract A virtual memory system comprising a main storage and a smaller high speed buffer. Current virtual-to-real address translations for both the main storage and the buffer are retained in a Storage Control and Address Translator (SCAT). The SCAT comprises a content addressable (associative) memory. The CPU-provided virtual address is used to interrogate the SCAT. If the data that is referenced by the virtual address is available in main storage, the SCAT will provide the main storage real address. If the data is also available in the buffer, the SCAT will provide the buffer real address.
Inventors
- 👤 R Ross
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 03:45
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
468 words
In a data processing system which contains a central processing unit, a main storage having n addressable locations each addressable by a real main storage address, a main storage address register, a buffer storage having fewer than n addressable locations each addressable by a real buffer storage address, a buffer storage address register, addressing means providing virtual addresses, and means for translating virtual addresses to real main storage and real buffer storage addresses, wherein each of said virtual addresses comprises a main storage virtual address, a buffer storage virtual address, a main storage real address portion and a buffer storage real address portion; an improved storage control and addressing means comprising: an associative memory comprising a plurality of words each of which contains a first interrogation field holding a main storage virtual address; a second interrogation field holding a buffer storage virtual address; a first result field holding the high-order bits of a main storage real address which corresponds to the main storage virtual address that is in said first interrogation field; and a second result field holding the high-order bits of a buffer storage real address which corresponds to the buffer storage virtual address that is in said second interrogation field; first means connected between said addressing means and said associative memory for transmitting said main storage virtual address to said associative memory, said main storage virtual address being subjected in said associative memory to a first comparison with the contents of said first interrogation field of said associative memory; second means connected between said addressing means and said associative memory for transmitting said buffer storage virtual address to said associative memory, said buffer storage virtual address being subjected in said associative memory to a second comparison with the contents of said second interrogation field of said associative memory; both of said comparisons occurring substantially simultaneously; said associative memory containing means responsive to an equal compare on said first comparison to cause a first readout of said first result field from a word in the associative memory in which the first interrogation field was equal to said main storage virtual address; said associative memory containing means responsive to an equal compare on said second comparison to cause a second readout of said second result field from a word in the associative memory in which the second interrogation field was equal to said buffer storage virtual address; means jointly responsive to the occurrence of bOth said first and second readouts to indicate that the data referenced by said addressing means is available in said buffer storage; and means jointly responsive to the occurrence of said first readout and the lack of said second readout to indicate that the data referenced by said addressing means is available in said main storage and is not available in said buffer storage.
Claim 2
Dependent Claim
468 words
In a data processing system which contains a central processing unit, a main storage having n addressable locations each addressable by a real main storage address, a main storage address register, a buffer storage having fewer than n addressable locations each addressable by a real buffer storage address, a buffer storage address register, addressing means providing virtual addresses, and means for translating virtual addresses to real main storage and real buffer storage addresses, wherein each of said virtual addresses comprises a main storage virtual address, a buffer storage virtual address, a main storage real address portion and a buffer storage real address portion; an improved storage control and addressing means comprising: an associative memory comprising a plurality of words each of which contains a first interrogation field holding a main storage virtual address; a second interrogation field holding a buffer storage virtual address; a first result field holding the high-order bits of a main storage real address which corresponds to the main storage virtual address that is in said first interrogation field; and a second result field holding the high-order bits of a buffer storage real address which corresponds to the buffer storage virtual address that is in said second interrogation field; first means connected between said addressing means and said associative memory for transmitting said main storage virtual address to said associative memory, said main storage virtual address being subjected in said associative memory to a first comparison with the contents of said first interrogation field of said associative memory; second means connected between said addressing means and said associative memory for transmitting said buffer storage virtual address to said associative memory, said buffer storage virtual address being subjected in said associative memory to a second comparison with the contents of said second interrogation field of said associative memory; both of said comparisons occurring substantially simultaneously; said associative memory containing means responsive to an equal compare on said first comparison to cause a first readout of said first result field from a word in the associative memory in which the first interrogation field was equal to said main storage virtual address; said associative memory containing means responsive to an equal compare on said second comparison to cause a second readout of said second result field from a word in the associative memory in which the second interrogation field was equal to said buffer storage virtual address; means jointly responsive to the occurrence of bOth said first and second readouts to indicate that the data referenced by said addressing means is available in said buffer storage; and means jointly responsive to the occurrence of said first readout and the lack of said second readout to indicate that the data referenced by said addressing means is available in said main storage and is not available in said buffer storage.
Claim 3
Dependent Claim
90 words
The storage control and addressing means of claim 1 further comprising: third means connected between said associative memory and said main storage address register to transmit the high-order bits of a main storage real address from said first result field to said main storage address register after said first readout; and fourth means connected between said associative memory and said buffer storage address register to transmit the high-order bits of a buffer storage real address from said second result field to said buffer storage address register after said second readout.
Claim 4
Dependent Claim
104 words
The storage control and addressing means of claim 2 wherein: said associative memory comprises a first associative memory containing said first interrogation field and said first result field, and a second associative memory containing said second interrogation field and said second result field; said first means is connected between said addressing means and said first associative memory; said second means is connected between said addressing means and said second associative memory; said third means is connected between said first associative memory and said main storage address register; and said fourth means is connected between said second associative memory and said buffer storage address register.
Claim 5
Dependent Claim
96 words
The storage control and addressing means of claim 3 wherein said associative memory further comprises: a single entry register for receiving said main storage virtual address and said buffer storage virtual address from said central processing unit; first gating means connected between said entry register and said first associative memory for transmitting said main storage virtual address to said first associative memory for said first comparison; and second gating means connected between said entry register and said second associative memory for transmitting said buffer storage virtual address to said second associative memory for said second comparison.
Claim 6
Dependent Claim
72 words
The storage control and addressing means of claim 1 wherein: said associative memory comprises a first associative memory containing said first interrogation field and said first result field, and a second associative memory containing said second interrogation field and said second result field; said first means is connected between said addressing means and said first associative memory; and said second means is connected between said addressing means and said second associative memory.
Claim 7
Dependent Claim
96 words
The storage control and addressing means of claim 5 wherein said associative memory further comprises: a single entry register for receiving said main storage virtual address and said buffer storage virtual address from said central processing unit; first masking means connected between said entry register and said first associative memory for transmitting said main storage virtual address to said first associative memory for said first comparison; and second masking means connected between said entry register and said second associative memory for transmitting said buffer storage virtual address to said second associative memory for said second comparison.
Claim 8
Dependent Claim
221 words
In a virtual storage system in which the virtual storage is divided into a predetermined number of pages with each page consisting of a plurality of blocks of data, a main storage for randomly storing page portions of said virtual storage, a buffer storage for storing block portions of said virtual storage, addressing means providing virtual address signals, with each virtual address having a page portion and a block portion; an improved storage control and addressing means comprising: an associative storage comprising a plurality of words each of which contains a virtual address part consisting of a page portion and a block portion, and a first associated real page address portion for addressing said main storage and a second associated real block address portion for addressing said buffer storage; means for simultaneously comparing the page portion of said address signals with corresponding portions of said words in said associative storage and comparing said block portion with corresponding portions of said words in said associative storage to produce a first signal resulting from equality of said first mentioned comparison and a second signal resulting from equality of said second mentioned comparison, said first signal indicating the availability in said main storage of an addressed page portion and said second signal indicating the availability in said buffer storage of an addressed block portion.
Claim 9
Dependent Claim
221 words
In a virtual storage system in which the virtual storage is divided into a predetermined number of pages with each page consisting of a plurality of blocks of data, a main storage for randomly storing page portions of said virtual storage, a buffer storage for storing block portions of said virtual storage, addressing means providing virtual address signals, with each virtual address having a page portion and a block portion; an improved storage control and addressing means comprising: an associative storage comprising a plurality of words each of which contains a virtual address part consisting of a page portion and a block portion, and a first associated real page address portion for addressing said main storage and a second associated real block address portion for addressing said buffer storage; means for simultaneously comparing the page portion of said address signals with corresponding portions of said words in said associative storage and comparing said block portion with corresponding portions of said words in said associative storage to produce a first signal resulting from equality of said first mentioned comparison and a second signal resulting from equality of said second mentioned comparison, said first signal indicating the availability in said main storage of an addressed page portion and said second signal indicating the availability in said buffer storage of an addressed block portion.
Claim 10
Dependent Claim
36 words
The storage control and addressing means of claim 7 further including: means responsive to said second signal for transferring said associated real block address to said buffer storage for subsequent use in addressing said buffer storage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-08 | 1977-04-09 | 1977-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-08 | 1981-04-09 | 1981-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-08 | 1985-04-09 | 1985-10-09 | $7700.00 | Window Closed / Lapsed |