Cache memory store in a processor of a data processing system

Claim 2

A processor in a data processing system including a backing memory store storing data and instructions in addressable storage locations, said processor comprising: a. operation means for performing arithmetic and logic functions on data and instructions retrieved from the backing memory store; b. processing means for processing data and instructions according to signals generated by said operation means and the data processing system; c. a communication control unit for controlling interface functions between the units of the processor and between the processor and the backing memory store in accordance with instructions processed by said processing means; d. a buffer register; e. a cache section including a cache store and means for storing data and instructions into addressable locations in said cache store; f. first switch means controlled by said communication control unit for controlling transfer of data information from said processing means to said buffer register and to said backing memory store; g. second switch means controlled by said communication control unit for selectively controlling transfer of data information from said backing memory store or said cache section to a third switch means and to said operations unit and said processing unit; and h. said third switch means controlled by said communication control unit for selectively controlling transfer of data information from said second switch means or said buffer register for storage in said cache store of said cache section; said third switch means operable in a store aside configuration to transfer the data information stored in said buffer register into said cache store if the address of the data information is in said cache section.

Claim 3

A processor as described in claim 1 further including means in said communication control unit for activating said second and third switch means to transfer data information from said backing memory store to said cache store to store a group of data and instruction words into said cache store without requiring further address signals from said processing means.

Claim 4

A processor as described in claim 1 wherein said cache section further includes a cache address register for storing a plurality of address signals obtained from said processing means for accessing data and instructions from said cache store, said cache address register queuing cache address signals to perform a series of cache store accesses.

Claim 5

A processor in a data processor system including a backing memory store storing data and instructions in addressable storage locations, said processor comprising: a. operation means for performing arithmetic and logic functions on data and instructions retrieved from the backing memory store; b. processing means for processing data and instructions according to signals generated by said operation means and the data processing system; c. a communication control unit for controlling interface functions between the units of the processor and between the processor and the backing memory store in accordance with instructions processed by said processing means; d. a buffer register; e. a cache section including a cache store and means for storing data and instructions into addressable locations in said cache store; f. first switch means controlled by said communication control unit for controlling transfer of data information from said processiNg means to said buffer register and to said backing memory store; g. second switch means controlled by said communication control unit for selectively controlling transfer of data information from said backing memory store or said cache section to a third switch means and to said operations unit and said processing unit; h. said third switch means controlled by said communication control unit for selectively controlling transfer of data information from said second switch means or said buffer register for storage in said cache store of said cache section; and i. means in said communication control unit for activating said second and third switch means to transfer data information from said backing memory store in said cache store to store a group of data and instruction words into said cache store without requiring further address signals from said processing means.

Claim 6

A processor in a data processor system including a backing memory store storing data and instructions in addressable storage locations, said processor comprising: a. operation means for performing arithmetic and logic functions on data and instructions retrieved from the backing memory store; b. processing means for processing data and instructions according to signals generated by said operation means and the data processing system; c. a communication control unit for controlling interface functions between the units of the processor and between the processor and the backing memory store in accordance with instructions processed by said processing means; d. a buffer register; e. a cache section including a cache store and means for storing data and instructions into addressable locations in said cache store; f. first switch means controlled by said communication control unit for controlling transfer of data information from said processiNg means to said buffer register and to said backing memory store; g. second switch means controlled by said communication control unit for selectively controlling transfer of data information from said backing memory store or said cache section to a third switch means and to said operations unit and said processing unit; h. said third switch means controlled by said communication control unit for selectively controlling transfer of data information from said second switch means or said buffer register for storage in said cache store of said cache section; and i. means in said communication control unit for activating said second and third switch means to transfer data information from said backing memory store in said cache store to store a group of data and instruction words into said cache store without requiring further address signals from said processing means.

Claim 7

A processor as described in claim 4 wherein said cache section further includes a cache address register for storing a plurality of address signals obtained from said processing means for accessing data and instructions from said cache store, said cache address register queuing cache address signals to perform a series of cache store accesses.

Claim 8

A processor in a data processing system including a backing memory store storing data and instructions in addressable storage locations, said processor comprising: a. operations means for performing arithmetic and logic functions on data and instructions retrieved from the backing memory store; b. processing means for processing data and instructions according to signals generated by said operation means and the data processing system; c. a communication control unit for controlling interface functions between the units of the processor and between the processor and the backing memory store in accordance with instructions processed by said processing means; d. a buffer register; e. a cache section including a cache store, and means including a cache address register for storing data and instructions into addressable locations in said cache store, said cache address register storing a plurality of address signals obtained from said processing means for accessing data and instructions from said cache store and for queuing cache address signals to perform a series of cache store accesses; f. first switch means controlled by said communication control unit for controlling transfer of data information from said processing means to said buffer register and to said backing memory store; g. second switch means controlled by said communication control unit for selectively controlling transfer of data information from said backing memory store or said cache section to a third switch means and to said operations unit and said processing unit; and h. said third switch means controlled by said communication control unit for selectively controlling transfer of data information from said second switch means or said buffer register for storage in said cache store of said cache section.

Claim 9

A processor in a data processing system including a backing memory store storing data and instructions in addressable storage locations, said processor comprising: a. operations means for performing arithmetic and logic functions on data and instructions retrieved from the backing memory store; b. processing means for processing data and instructions according to signals generated by said operation means and the data processing system; c. a communication control unit for controlling interface functions between the units of the processor and between the processor and the backing memory store in accordance with instructions processed by said processing means; d. a buffer register; e. a cache section including a cache store, and means including a cache address register for storing data and instructions into addressable locations in said cache store, said cache address register storing a plurality of address signals obtained from said processing means for accessing data and instructions from said cache store and for queuing cache address signals to perform a series of cache store accesses; f. first switch means controlled by said communication control unit for controlling transfer of data information from said processing means to said buffer register and to said backing memory store; g. second switch means controlled by said communication control unit for selectively controlling transfer of data information from said backing memory store or said cache section to a third switch means and to said operations unit and said processing unit; and h. said third switch means controlled by said communication control unit for selectively controlling transfer of data information from said second switch means or said buffer register for storage in said cache store of said cache section.

Claim 10

A processor in a data processing system including a backing memory store storing data and instructions in addressable storage locations, said processor comprising: a. operation means for performing arithmetic and logic functions on data and instructions retrieved from the backing memory store; b. processing means for processing data and instructions according to signals generated by said operation means and the data processing system; c. a communication control unit for controlling interface functions between the units of the processor and between the processor and the backing memory store in accordance with instructions processed by said processing means; d. a buffer register; e. a cache section including a cache store, and means including a cache address register for storing data and instructions into addressable locations in said cache store, said cache address register storing a plurality of address Signals obtained from said processing means for accessing data and instructions from said cache store and for queuing cache address signals to perform a series of cache store accesses; f. first switch means controlled by said communication control unit for controlling transfer of data information from said processing means to said buffer register and to said backing memory store; g. second switch means controlled by said communication control unit for selectively controlling transfer of data information from said backing memory store or said cache section to a third switch means and to said operations unit and said processing unit; h. said third switch means controlled by said communication control unit for selectively controlling transfer of data information from said second switch means or said buffer register for storage in said cache store of said cache section; said third switch means operable in a store aside configuration to transfer the data information stored in said buffer register into said cache store if the address of the data information is in said cache section; i. means in said communication control unit for activating said second and third switch means to transfer data information from said backing memory store to said cache store to store a group of data and instruction words into said cache store without requiring further address signals from said processing means.

Claim 11

A processor in a data processing system including a backing memory store storing data and instructions in addressable storage locations, said processor comprising: a. operation means for performing arithmetic and logic functions on data and instructions retrieved from the backing memory store; b. processing means for processing data and instructions according to signals generated by said operation means and the data processing system; c. a communication control unit for controlling interface functions between the units of the processor and between the processor and the backing memory store in accordance with instructions processed by said processing means; d. a buffer register; e. a cache section including a cache store, and means including a cache address register for storing data and instructions into addressable locations in said cache store, said cache address register storing a plurality of address Signals obtained from said processing means for accessing data and instructions from said cache store and for queuing cache address signals to perform a series of cache store accesses; f. first switch means controlled by said communication control unit for controlling transfer of data information from said processing means to said buffer register and to said backing memory store; g. second switch means controlled by said communication control unit for selectively controlling transfer of data information from said backing memory store or said cache section to a third switch means and to said operations unit and said processing unit; h. said third switch means controlled by said communication control unit for selectively controlling transfer of data information from said second switch means or said buffer register for storage in said cache store of said cache section; said third switch means operable in a store aside configuration to transfer the data information stored in said buffer register into said cache store if the address of the data information is in said cache section; i. means in said communication control unit for activating said second and third switch means to transfer data information from said backing memory store to said cache store to store a group of data and instruction words into said cache store without requiring further address signals from said processing means.