Integrated memory system with block transfer to a buffer store

Abstract

Abstract A DATA PROCESSING SYSTEM HAS A MEMORY HIERARCHY INCLUDING A HIGH-SPEED LOW-CAPACITY BUFFER STORE (BS) LOCATED BETWEEN A CENTRAL PROCESSING ELEMENT (CPE) AND A LOW SPEED HIGH-CAPACITY MAIN STORE (MS). MEMORY ACCESSING, TO STORE DATA IN OR FETCH DATA FROM AN ADDRESSED WORK LOCATION, BY THE CPE AND BY CHANNELS IS CONTROLLED BY A STORAGE CONTROL UNIT (SCU). ADDRESSES SPECIFIED REFER TO MS WORK LOCATIONS. FOR CPE ACCESS REQUESTS, A TEST IS MADE TO DETEMINED WHETHER THE CONTENT OF THE MS ADDRESSED LOCATION IS RESIDENT IN THE BS. IF IT IS, THEN A STORE IS MADE IN BOTH THE BS AND MS WHILE A FETCH IS MADE ONLY FROM THE BS. IF THE ADDRESSED WORD LOCATION IS NOT RESIDENT IN THE BS, THEN A STORE IS MADE ONLY IN MS AND A FETCH IS MADE FROM THE ADDRESSED LOCATION OF MS. THE DATA FETCHED FROM THE ADDRESSED MS LOCATION IS TRANSFERRED TO THE CPE AND LOADED IN A WORD LOCATION OF THE BS. WHEN SUCH A FETCH IS MADE TO MS, THE SCU ALSO FETCHES ADDITIONAL WORDS, CONTIGUOUS TO THE ADDRESSED WORD, TO FORM A BLOCK AND LOADS THE BLOCK IN THE BS. OVERLAPPING OPERATION ALLOWS A PLURALITY OF BLOCK TRANSFER FROM MS TO BE INITIATED BY THE SCU FOR SUCCESSIVE ACCESS REQUESTS WHICH FIND THE ADDRESSED LOCATIONS NONRESIDENT IN THE BS. CHANNEL REQUESTS ACCESS ONLY THE MS. ASSOCIATED WITH EACH BLOCK OF WORDS IN BS IS A VALID BIT WHICH PERMITS ACCESS TO WORDS IN BS ONLY WHEN SET. DURING A CHANNEL STORE, IF THE ADDRESSED LOCATION IS IN THE BS, THE VALID BIT ASSOCIATED WITH THAT LOCATION IS RESET SIGNIFYING THAT THE DATA CONTENT OF THE CORRESPONDING MS LOCATION HAS BEEN CHANGED.

Inventors

• 👤 Lawrence J Boland
• 👤 Gerry D Granito

Bibliographic Details