Computer system having an extended directly addressable memory space

Claim 1

A computer system comprising central processing means (10) random access memory means (12), memory management means (11); and bus means (17) interconnecting said central processor means, said random access memory means and said memory management means, comprising: said random access memory means having a sequence of word locations of equal length, each location accommodating a word, a predetermined fraction of said word locations containing two character locations of equal length, each location accommodating a character being half as long as a word, said random access memory means being connected to said bus means by means of an address input (MAD 00--MAD 15), a bidirectional data line (BIO 00-BIO 15), a character selection signal (CHA) input, and a handshake interconnection (TMRX, TRMN); said central processing means being connected to said bus means by means of an address output (MAD 00--MAD 15), a bidirectional data line (BIO 00-BIO 15), a character selection signal (CHA) output, and a handshake interconnection; said central processing means having address generating means for generating N-bit addresses on said address output, and first signalling means for generating a character detection signal, a first value of said character detection signal signalling that an accompanying address is directed to a word location as one of 2 N different word locations; a second value of said character selection signal signalling that an accompanying address is directed to a character location, in that one predetermined address bit operates as first/second character location selecting bit, the remaining (N-1) bits then operating to select a word location in one predetermined half of said 2 N different word locations; said memory management means being connected to said bus means by means of an address input (MAD 00 . . . MAD 15), a bidirectional data line (BIO 00-BIO 15) and a handshake interconnection, said memory management means being connected to said central processing means by means of a segment table pointer line (13), said memory management means being connected to said random access memory means by means of a physical page number line (16) for forwarding a page selection signal.