Computer with dual vat buffers for accessing a common memory shared by a cache and a processor interrupt stack

Claim 2

A computer system comprising: a processor (101) generating and transmitting virtual address signals, mode control signals and read control signals; main memory means (104); buffer memory means (110, 111, 112, 113); and address translation means (102, 118) responsive to said virtual address signals for generating real address signals for said main memory means and said buffer memory means; characterized in that said buffer memory means comprises a cache memory portion having a plurality of cache memory locations and an interrupt stack portion having a plurality of interrupt stack memory locations; said address translation means is responsive to certain of said virtual address signals for generating real address signals of a first set for accessing said main memory and said cache memory portion and responsive to others of said virtual address signals for generating real address signals of a second set and a select signal; and said buffer memory means is responsive to real address signals of said first set to selectively access said cache memory locations and responsive to real address signals of said second set and said select signal to access said interrupt stack locations.

Claim 3

A computer system in accordance with claim 1 further characterized in that said address translation means comprises a first address translation buffer means (102) responsive to said certain virtual address signals for generating said real address signals of said first set and a second address translation buffer (118) responsive to said other virtual address signals to generate real address signals of said second set and said select signal.

Claim 4

A computer system in accordance with claim 2 characterized in that said second address translation buffer means comprises a register means (302) and a comparison means (303) responsive to contents of said register means and said others of said virtual address signals to generate said select signal if contents of said register means is identical to any of said others of said virtual address signals.

Claim 5

A computer system in accordance with claim 3 wherein said processor is further adapted to generate and to transmit a write control signal and a control word characterized in that said register means is responsive to said write control signal to store said control word to said register means.

Claim 6

A computer system in accordance with claim 1 further characterized in that said cache memory portion further comprises a tag memory means (112), cache control means (110), comparison means (113), and data memory means (111); said virtual address signals further comprise segment address signals, page address signals and word address signals; said address translation means is responsive to said segment address signals and said page address signals of said certain of said address signals to generate said significant address signals; said real address signals of said first set further comprise said significant address signals and said word address signals; said tag memory and said data memory means being responsive to said read control signals and said word address signals to read a first and a second data word; said comparison means being responsive to said significant address signals and said first data word to generate and to transmit to said cache control means a first cache signal if said significant address signals equal said first data word; said cache control means being responsive to said first cache signal to generate and to transmit a second cache signal to said data memory means; and said data memory means being responsive to said second cache signal to transmit said second data word to said processor.

Claim 7

A computer system in accordance with claim 2 characterized in that said first address translation buffer is responsive to said select signal to inhibit the generation of said real address signals.

Claim 8

A computer system comprising: a processor generating and transmitting virtual address signals, mode control signals, and read control signals; main memory means; buffer memory means; cache controller means; and address translation means responsive to said virtual address signals for generating real address signals for said main memory means and said buffer memory means; said buffer memory means comprises a cache memory portion having a plurality of cache memory locations and an interrupt stack portion having a plurality of interrupt stack memory locations; said address translation means is responsive to certain of said virtual address signals for generating real address signals of a first set for accessing said main memory and said cache memory portion and responsive to others of said virtual address signals for generating real address signals of a second set and a select signal; said cache controller means responsive to said virtual address signals to generate cache control signals; and said buffer memory means is responsive to real address signals of said first set and said cache control signals to selectively access said cache memory locations and responsive to real address signals of said second set and said select signal to access said interrupt stack locations.

Claim 9

A computer system comprising: a processor generating and transmitting virtual address signals, mode control signals, and read control signals; main memory means; buffer memory means; cache controller means; and address translation means responsive to said virtual address signals for generating real address signals for said main memory means and said buffer memory means; said buffer memory means comprises a cache memory portion having a plurality of cache memory locations and an interrupt stack portion having a plurality of interrupt stack memory locations; said address translation means is responsive to certain of said virtual address signals for generating real address signals of a first set for accessing said main memory and said cache memory portion and responsive to others of said virtual address signals for generating real address signals of a second set and a select signal; said cache controller means responsive to said virtual address signals to generate cache control signals; and said buffer memory means is responsive to real address signals of said first set and said cache control signals to selectively access said cache memory locations and responsive to real address signals of said second set and said select signal to access said interrupt stack locations.

Claim 10

A computer system in accordance with claim 7 wherein said address translation means comprises a first address translation buffer means responsive to said certain virtual address signals for generating said real address signals of said first set and a second address translation buffer responsive to said other virtual address signals to generate real address signals of said second set and said select signal.

Claim 11

A data processing system in accordance with claim 8 wherein said second address translation buffer means comprises register means and comparison means responsive to contents of said register means and said other virtual address signals to generate said select signal if contents of said register means is identical to any of said other virtual address signals.

Claim 12

A data processing system in accordance with claim 9 wherein said processor is further adapted to generate and to transmit a write control signal and a control word; and said register means is responsive to said write control signal to store said control word to said register means.

Claim 13

A data processing system in accordance with claim 8 wherein said first address translation buffer is responsive to said select signal to inhibit the generation of said real address signals.