US4727484A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory address control apparatus with separate translation look aside buffers for a data processor using a virtual memory technique
Assignee: NEC Corp
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Filing: 1986-12-24
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Granted: 1988-02-23
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Expires: 2006-12-24
Abstract
Abstract A memory control apparatus for a data processor using a virtual memory technique includes two cache memories one for storing a portion of the instructions located in the main memory (MMU), the other for storing a portion of the operand data located in main memory. A separate translation look aside buffer (TLB) is connected to each cache memory, with the TLB connected to the cache memory storing instructions operating to translate logical addresses to real addresses in the MMU storing instructions, while the TLB connected to the cache memory storing operand data operating to translate logical addresses to real addresses in the MMU storing operand data.
Inventors
- 👤 Masato Saito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:19
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
121 words
In a data processing system memory address control apparatus connected to a main memory unit (MMU) and a processing unit (PU) including an instruction fetch unit, an operand fetch unit, and an execution unit, said control apparatus comprising: instruction address translation means coupled to said instruction fetch unit for translating exclusively logical addresses for reading out instruction words stored in the MMU into corresponding real addresses of the MMU; and operand data address translation means coupled to said operand fetch unit for translating exclusively logical addresses for reading out data words stored in the MMU into corresponding real addresses of the MMU; wherein the instruction address translation operation and the operand data address translation operation are performed in parallel and simultaneously.
Claim 2
Dependent Claim
121 words
In a data processing system memory address control apparatus connected to a main memory unit (MMU) and a processing unit (PU) including an instruction fetch unit, an operand fetch unit, and an execution unit, said control apparatus comprising: instruction address translation means coupled to said instruction fetch unit for translating exclusively logical addresses for reading out instruction words stored in the MMU into corresponding real addresses of the MMU; and operand data address translation means coupled to said operand fetch unit for translating exclusively logical addresses for reading out data words stored in the MMU into corresponding real addresses of the MMU; wherein the instruction address translation operation and the operand data address translation operation are performed in parallel and simultaneously.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-22 | 1991-08-24 | 1992-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-22 | 1995-08-24 | 1996-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-22 | 1999-08-24 | 2000-02-23 | $7700.00 | Window Closed / Lapsed |