US4635194A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Instruction buffer bypass apparatus
Assignee: International Business Machines Corp
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Filing: 1983-05-02
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Granted: 1987-01-06
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Expires: 2003-05-02
Abstract
Abstract A bypass apparatus in a computer system is disclosed. The computer system includes a central storage facility for storing various instructions to be executed, an instruction register for storing an instruction being executed, and an instruction buffer, interconnected between the central storage facility and the instruction register, for temporarily storing the next instructions to be executed following execution of the instruction stored in the instruction register. A bypass path interconnects the central storage facility directly to the instruction register for bypassing the instruction buffer when certain special instructions being held in the instruction register are being executed, such as an EXECUTE instruction. Consequently, the contents of the instruction buffer are not lost or destroyed as a result of execution of the special instruction. The computer system further includes an execute register interconnected between the central storage facility and the instruction register for storing one or more bytes of the instruction being executed when the byte-length of the instruction is greater than the byte-length of the instruction register which stores said instruction.
Inventors
- 👤 Mark E. Burger
- 👤 Steven L. George
- 👤 Chuck H. Ngai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 23:41
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30181; G06F9/30145; G06F9/30149; G06F9/30185; G06F9/32; G06F9/322; G06F9/38; G06F9/3802; G06F9/3816
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
216 words
In a computer system including a central storage facility for storing a plurality of instructions and at least one special instruction, an instruction buffer connected to the central storage facility for retrieving each of the plurality of instructions and said special instruction in sequence form said storage facility, and an instruction register connected to the instruction buffer for retrieving an instruction from the instruction buffer and holding at least some of the bytes of said instruction therein during execution thereof, the improvement comprising: bypass path means connected between said central storage facility and said instruction register for bypassing said instruction buffer when the special instruction is held in said instruction register for execution, another instruction being transferred from said central storage facility to said instruction register via said bypass path means during execution of said special instruction thereby bypassng said instruction buffer and preventing the destruction of the contents of said buffer; and execute register means connected between said central storage facility and said instruction register for storing one or more additional bytes of said another instruction during the transfer of said another instruction from said central storage facility to said instruction register via said bypass path means when the byte length of said another instruction is greater than the byte length of said instruction register.
Claim 2
Dependent Claim
216 words
In a computer system including a central storage facility for storing a plurality of instructions and at least one special instruction, an instruction buffer connected to the central storage facility for retrieving each of the plurality of instructions and said special instruction in sequence form said storage facility, and an instruction register connected to the instruction buffer for retrieving an instruction from the instruction buffer and holding at least some of the bytes of said instruction therein during execution thereof, the improvement comprising: bypass path means connected between said central storage facility and said instruction register for bypassing said instruction buffer when the special instruction is held in said instruction register for execution, another instruction being transferred from said central storage facility to said instruction register via said bypass path means during execution of said special instruction thereby bypassng said instruction buffer and preventing the destruction of the contents of said buffer; and execute register means connected between said central storage facility and said instruction register for storing one or more additional bytes of said another instruction during the transfer of said another instruction from said central storage facility to said instruction register via said bypass path means when the byte length of said another instruction is greater than the byte length of said instruction register.
Claim 3
Dependent Claim
100 words
In the computer system of claim 1, further comprising: byte-shifter means interconnecting said instruction buffer and said instruction register to said central storage facility for shifting the bytes of said instruction received from said central storage facility by a predetermined amount prior to the holding of said some of the bytes of said instruction in said instruction register and the storage of said one or more additional bytes in said execute register means, the magnitude of said predetermined amount depending upon the magnitude of a set of bits which comprise at least a portion of the address of said instruction.
Claim 4
Dependent Claim
49 words
In the computer system of claim 2, wherein said bypass path means comprises an instruction transfer path connecting said byte shifter means to said instruction register and bypassing said instruction buffer, said instruction transfer path being enabled when said special instruction is stored in said instruction register for execution.
Claim 5
Dependent Claim
238 words
A computer system, comprising: a central storage facility for storing a plurality of instructions to be executed; register means for holding one of said instructions therein for execution; processor means connected to said register means for receiving and executing the one instruction stored in said register means; buffer means interconnected between said central storage facility and said register means for storing a next instruction of a sequence of instructions, said register means receiving and holding said next instruction when execution of said one instruction by said processor means is complete; bypass means connecting said central storage facility to said register means by passing said buffer means when a special instruction in said sequence of instructions is held in said register means for execution by said processor means, another instruction not a part of said sequence being retrieved from said central storage facility and transferred to said register means via said bypass means thereby preserving the contents of said buffer means; and execute register means interconnected between said central storage facility and said register means for storing one or more bytes of said another instruction during the transfer of said another instruction from said central storage facility to said register means via said bypass means thereby permitting the storage of the remaining bytes of said another instruction in said register means when the byte length of said another instruction is greater than the byte length of said register means.
Claim 6
Dependent Claim
238 words
A computer system, comprising: a central storage facility for storing a plurality of instructions to be executed; register means for holding one of said instructions therein for execution; processor means connected to said register means for receiving and executing the one instruction stored in said register means; buffer means interconnected between said central storage facility and said register means for storing a next instruction of a sequence of instructions, said register means receiving and holding said next instruction when execution of said one instruction by said processor means is complete; bypass means connecting said central storage facility to said register means by passing said buffer means when a special instruction in said sequence of instructions is held in said register means for execution by said processor means, another instruction not a part of said sequence being retrieved from said central storage facility and transferred to said register means via said bypass means thereby preserving the contents of said buffer means; and execute register means interconnected between said central storage facility and said register means for storing one or more bytes of said another instruction during the transfer of said another instruction from said central storage facility to said register means via said bypass means thereby permitting the storage of the remaining bytes of said another instruction in said register means when the byte length of said another instruction is greater than the byte length of said register means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-05 | 1990-07-07 | 1991-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-05 | 1994-07-07 | 1995-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-05 | 1998-07-07 | 1999-01-06 | $7700.00 | Window Closed / Lapsed |