Cache unit bypass apparatus

Claim 2

A data processing system comprising: an addressable main store having a plurality of word locations for storing information including data and instructions; a cache unit coupled to said main store for providing immediate access to data and instruction words fetched from said main store, said cache unit including a buffer store having a plurality of addressable locations, and said cache unit including control means for fetching said data and instruction words from said main store in response to command signals; and, processing means coupled to said buffer store, said processing means for processing instructions fetched from said main store, each instruction including an operation code portion, said processing means including control means for generating signals including memory commands required for the execution of said instructions, said processing control means including decoder circuit means responsive to signals indicative of an operation code portion coded to specify a predetermined class of instruction to generate coded command signals specifying the fetching of a segment of data words from said cache unit; and, said cache unit further including: decoder circuit means coupled to said processing means; indicator circuit means coupled to said decoder circuit means, said cache decoder circuit means in response to a first set of said coded command signals to switch said indicator circuit means to a predetermined state; and, bistable control means coupled to said indicator means and to said cache decoder circuit means, said bistable control means being conditioned by said cache decoder circuit means in response to a succeeding set of coded command signals to switch to said predetermined state when said segment of data words is not stored in said buffer store and said indicator circuit means is in said predetermined state for inhibiting other segments of data words fetched from said main store in response to said predetermined class of instruction from being stored in said buffer store.

Claim 3

The system of claim 1 wherein each instruction further includes a number of address portions and wherein said main store is organized into a plurality of sets of blocks of word locations, said processing control means being operative to generate memory command signals accompanying said command signals, said coded memory command signals including a command code specifying the type of main store read operation and an address generated from one of said address portions specifying the data word to be fetched from said cache unit and said processing decoder circuit means including circuit means operative to generate signals corresponding to said command code coded to specify the fetching of a block of data words corresponding to said segment including said data word specified by said command address from said main store.

Claim 4

The system of claim 2 wherein said processing control means further includes means operative to generate a number of sets of said coded command signals in response to said operation code portion, each set specifying the fetching of said block of data words.

Claim 5

The system of claim 3, wherein said number of sets of said coded command signals varies in accordance with the number of data words defining a pair of data strings specified by first and second ones of said number of address portions to be operated upon as specified by said operation code portion.

Claim 6

The system of claim 4 wherein said operation code portion is coded to specify a move operation.

Claim 7

The system of claim 1 wherein said buffer store comprises a plurality of word locations organized into a plurality of levels, each for storing a number of blocks of words of said information and said cache unit further includes: a directory for storing block addresses identifying the blocks of words stored within said buffer store levels, said directory including a plurality of locations, each of said locations including a plurality of bit positions for storing level assignment signals identifying a next level within said buffer store into which new information fetched from said main store is to be placed; and, replacement circuit means for generating said level assignment signals in a predetermined pattern, said replacement circuit means being coupled to said directory and to said bistable control means, said directory being conditioned by said bistable control means when in said predetermined state to prevent assigning the level specified by said level assignment signals.

Claim 8

The system of claim 6 wherein said cache unit further includes: comparison means coupled to said directory and to said processing means for comparing said block addresses read from said directory with the high order portion of said command address and generating a hit-miss signal indicative of whether or not the data word being requested is stored in said buffer store; and, gating means coupled to said comparison means, said indicator circuit means, said cache decoder circuit means and to said bistable control means, said gating means logically combining said hit-miss signal with signals from said indicator circuit means and said cache decoder circuit means for conditioning said bistable control means to switch to said predetermined state.

Claim 9

The system of claim 6 wherein said cache unit further includes: an address register including a number of bit positions for storing an address of a next data word to be accessed by said processing means; a data buffer coupled to said main store, said buffer comprising a plurality of addressable locations for storing a segment of data consisting of a number of data words, each location for storing a data word and an indicator signal for designating when said word had been stored therein; and, compare circuit means coupled to said address register and to said data buffer, said compare circuit means for enabling the transfer of requested data words to said processing means upon detecting that the data word specified by the address contents of said address register has been received from said main store and is being written into one of said data buffer locations.

Claim 10

The system of claim 6 wherein said replacement circuit means includes: a register coupled to said directory for storing said level assignment signals read out therefrom; and, increment circuit means for generating sequences of level assignment signals, said increment circuit means being coupled to said register and to said directory, said increment circuit means being operative to modify said level assignment signals by incrementing them by one skipping over the assignment of that level.

Claim 11

The system of claim 9 wherein said directory further includes a section having a plurality of addressable levels corresponding in number to said number of buffer store levels, each level including a plurality of locations for storing said block addresses, said cache unit further including: first decoder circuit means having a plurality of input terminals coupled to receive said level assignment signals from said register of said replacement circuit means, an enabling input terminal coupled to said bistable control means and a plurality of output terminals for applying read/write control signals to said directory levels, said first decoder circuit means being conditioned by said bistable control means when in said predetermined state from generating said read/write control signals in response to said level assignment signals inhibiting the storage of a second portion of said command address into the level designated by said level assignment signals preventing said assignment of said level.

Claim 12

The system of claim 10 wherein said cache unit further includes: write flag indicator means coupled to said bistable control means, said write flag indicator means for storing an indication specifying when a requested segment of data words is to be written into one of said buffer store levels; and, memory write control means coupled to said buffer store and to said write flag indicator means, said write control means for generating signals for enabling said segment of data words received from said main store to be written into said one level, said bistable control means when in said predetermined state inhibiting said write flag indicator means from storing said indication for preventing said memory write control means from generating said signals for writing said segment into said buffer store level.

Claim 13

The system of claim 1 wherein said processing control means further includes microprogram control means including: an addressable address store coupled to receive signals corresponding to said operation code portion, said address store including a plurality of locations, each for storing a word including at least a first address identifying a first microinstruction of a different one of a plurality of execution sequences and an output register connected to said address store for storing the word contents of a location specified by said operation code portion; and, a cycled addressable control store including a plurality of locations storing at least one microinstruction of a different one of said plurality of execution sequences required for controlling the operation of said processing means during the execution of said instructions and an output register connected to said control store and to said processing decoder circuit means, said control store output register for temporarily storing the microinstruction contents of an accessed location during a cycle of operation of said control store, one of said plurality of execution sequences including a number of microinstructions coded for conditioning said processing unit during execution of the operation specified by said operation code portion specifying said predetermined class of instruction, each of said microinstructions including a number of fields, at least one of said number of fields being used to specify cache commands and said processing decoder circuit means being coupled to said control store output register and operative in response to signals from said one field of each microinstruction read out to said control store output register containing a predetermined code to generate said coded command signals specifying said fetching of a segment of data words.

Claim 14

The system of claim 12 wherein said microprogram control means further includes branch control means coupled to a number of indicator storage circuits and coupled to said control store for conditioning said control store to branch to microinstructions within said sequence in accordance with signals corresponding to the states of said indicator storage circuits and said branch control means in response to a signal from a predetermined one of said indicator storage circuits to condition said control store to branch to a location within said control store for terminating the execution of said instruction.

Claim 15

The system of claim 13 wherein said system further includes interface signalling means coupled to said predetermined one of said indicator storage circuits and to said indicator circuit means, said predetermined one of said indicator storage circuits when switched to said predetermined state conditioning said indicator circuit means to switch from said predetermined state to a reset state.

Claim 16

A data processing system comprising: a main store including a plurality of word locations for storing data and instructions; a processing unit coupled to said main store for processing instructions received therefrom, each instruction including an operation code, said processing unit including control means for generating signals including memory commands required for the execution of said instructions, said control means including decoder circuit means responsive to signals indicative of an operation code specifying a predetermined class of instruction to generate cache command signals coded to specify fetching a segment of data words from said main store; a cache unit operatively coupled to said main store for providing said processing unit with immediate access to said data and instructions fetched from said main store, said cache unit being coupled to said processing unit and including: a buffer store including a plurality of addressable word locations arranged into a plurality of levels for storing said data and instructions, each level containing a number of blocks of said word locations; a directory including a plurality of locations corresponding in number to the number of levels in said buffer store, each location of said directory storing block addresses identifying the blocks of words stored within a corresponding one of said buffer store levels; comparison means coupled to said directory for comparing said block addresses read from said directory with a first portion of a command address accompanying said cache command signals and generating a hit-miss detection signal indicating whether or not the data word being requested by said processing unit is stored in said buffer store; detection means coupled to said directory, to said comparison means and to said processing unit, said detection means generating an output signal in response to a predetermined number of sets of said cache command signals when said hit-miss detection signal indicates a miss condition, said output signal indicating that said processing unit is executing said predetermined class of instruction; and, said directory being inhibited by said output signal from storing second portions of the command addresses associated with predetermined ones of said predetermined number of sets of said cache command signals preventing a flushing of the contents of a substantial number of said plurality of locations of said buffer store with segments of data words fetched in response to said predetermined class of instruction.

Claim 17

A data processing system comprising: a main store including a plurality of word locations for storing data and instructions; a processing unit coupled to said main store for processing instructions received therefrom, each instruction including an operation code, said processing unit including control means for generating signals including memory commands required for the execution of said instructions, said control means including decoder circuit means responsive to signals indicative of an operation code specifying a predetermined class of instruction to generate cache command signals coded to specify fetching a segment of data words from said main store; a cache unit operatively coupled to said main store for providing said processing unit with immediate access to said data and instructions fetched from said main store, said cache unit being coupled to said processing unit and including: a buffer store including a plurality of addressable word locations arranged into a plurality of levels for storing said data and instructions, each level containing a number of blocks of said word locations; a directory including a plurality of locations corresponding in number to the number of levels in said buffer store, each location of said directory storing block addresses identifying the blocks of words stored within a corresponding one of said buffer store levels; comparison means coupled to said directory for comparing said block addresses read from said directory with a first portion of a command address accompanying said cache command signals and generating a hit-miss detection signal indicating whether or not the data word being requested by said processing unit is stored in said buffer store; detection means coupled to said directory, to said comparison means and to said processing unit, said detection means generating an output signal in response to a predetermined number of sets of said cache command signals when said hit-miss detection signal indicates a miss condition, said output signal indicating that said processing unit is executing said predetermined class of instruction; and, said directory being inhibited by said output signal from storing second portions of the command addresses associated with predetermined ones of said predetermined number of sets of said cache command signals preventing a flushing of the contents of a substantial number of said plurality of locations of said buffer store with segments of data words fetched in response to said predetermined class of instruction.

Claim 18

The system of claim 15 wherein said detection means comprises: decoder means coupled to said processing unit; indicator circuit means coupled to said decoder means, said indicator circuit means being switched from a first state to a second state by said decoder means in response to a predetermined one of said predetermined number of sets of said cache command signals; and, bistable control means coupled to said indicator means, to said decoder means and to said comparison means, said bistable control means being conditioned by said decoder means in response to another one of said predetermined number of sets of cache command signals when conditioned by said hit-miss detection signal indicating said miss condition to switch from said first to said second state for generating said output signal.

Claim 19

The system of claim 16 wherein said predetermined number of said sets of said cache command signals represents replacement of the contents of a number of locations of said buffer store sufficient to accommodate short move operations.

Claim 20

The system of claim 17 wherein said predetermined number is two and each set of said cache command signals is coded to specify a load quad operation.

Claim 21

The system of claim 17 wherein said number of said locations provides storage for at least sixteen characters.

Claim 22

The system of claim 15 wherein each instruction within said class further includes a number of address portions, said processing unit control means including means operative to generate memory command signals accompanying said cache command signals, said memory command signals including a command code specifying the type of main store read operation and said command address generated from one of said address portions specifying the data word to be fetched from said cache unit.

Claim 23

The system of claim 20 wherein the number of sets of said cache command signals varies in accordance with the number of data words defining a pair of data strings specified by first and second ones of said number of address portions to be operated upon as specified by said operation code portion of said instruction.

Claim 24

The system of claim 15 wherein each of said locations of said directory includes a plurality of bit positions for storing level assignment signals identifying a next level within said buffer store into which a segment of data words fetched from said main store is to be placed; and, wherein said cache unit further includes: replacement circuit means for generating said level assignment signals in a predetermined pattern, said replacement circuit means being coupled to said directory and to said detection means, said directory being conditioned by said output signal from said detection means to prevent assignment of the level specified by said level assignment signals.

Claim 25

The system of claim 22 wherein said cache unit further includes: an address register including a number of bit positions for storing an address of a next data word to be accessed by said processing unit. a data buffer coupled to said main store, said buffer comprising a plurality of addressable locations for storing a segment of data words, each location for storing a data word and an indicator signal for designating when a data word had been stored therein; and, compare circuit means coupled to said address register and to said data buffer, said compare circuit means for enabling the transfer of requested data words to said processing means upon detecting that the data word sepcified by the address contents of said address register has been received from said main store and is being written into one of said data buffer locations.

Claim 26

The system of claim 23 wherein said cache unit further includes: write flag indicator means coupled to said detection means, said write flag indicator means for storing an indication specifying when a requested segment of data words is to be written into one of said buffer store levels; and, memory write control means coupled to said buffer store and to said write flag indicator means, said write control means for generating signals for enabling said segment of data words received from said main store to be written into said one level, said output signal from said detection means inhibiting said write flag indicator means from storing said indication for preventing said memory write control means for generating said signals for writing said segment into said buffer store level.

Claim 27

The system of claim 15 wherein said control means further includes microprogram control means including: an addressable address store coupled to receive signals corresponding to said operation code, said address store including a plurality of locations, each for storing a word including at least a first address identifying a first microinstruction of a different one of a plurality of execution sequences and an output register connected to said address store for storing the word contents of a location specified by said operation code; and, a cycled addressable control store including a plurality of locations storing at least one microinstruction of a different one of said plurality of execution sequences required for controlling the operation of said processing unit during the execution of said instructions and an output register connected to said control store and to said decoder circuit means, said control store output register for temporarily storing the microinstruction contents of an accessed location during a cycle of operation of said control store, one of said plurality of execution sequences including a number of microinstructions coded for conditioning said processing unit during execution of the operation specified by said operation code specifying said predetermined class of instruction, each of said microinstructions including a number of fields, at least one of said number of fields being used to specify cache commands and said processing decoder circuit means being coupled to said control store output register and operative in response to signals from said one field of each microinstruction read out from said control store containing a predetermined code to generate said coded command signals specifying said fetching of a segment of data words.

Claim 28

The system of claim 25 wherein said microprogram control means further includes branch control means coupled to a number of indicator storage circuits and coupled to said control store for conditioning said control store to branch to microinstructions within said sequence in accordance with signals corresponding to the states of said indicator storage circuits and said branch control means in response to a signal from a predetermined one of said indicator storage circuits to condition said control store to branch to a location within said control store for terminating the execution of said instruction.

Claim 29

The system of claim 26 wherein said system further includes interface signalling means coupled to said predetermined one of said indicator storage circuits and to said detection means, said predetermined one of said indicator storage circuits when switched to said predetermined state conditioning said detection means for the processing of a next instruction.

Claim 30

A data processing system comprising: a main store including a plurality of word locations for storing data and instruction words; a cache unit operatively coupled to said main store for providing immediate access to said data and instruction words fetched from said main store in response to commands received from a processing unit including a command code and an address, said cache unit including: a buffer store including a plurality of addressable word locations arranged into a plurality of levels, each level containing a number of blocks of said word locations; an addressable directory having a plurality of locations corresponding in number to the number of levels in said buffer store, each location of said directory storing block addresses identifying the blocks of words within a corresponding one of said buffer store levels; comparison means coupled to said directory for comparing said block addresses read from said directory in response to said address of each of said commands and generating a hit-miss detection signal indicating whether or not the data word being requested is stored in said buffer store; and, said processing unit for processing instructions received from said main store, each instruction including an operation code, said processing unit being coupled to said cache unit for transferring and receiving information to and from said cache unit during the execution of said instructions, said processing unit including: control means for generating signals including cache command signals and said memory commands required for the execution of said instructions, said control means including: a plurality of registers for storing instructions received from said cache unit to be processed; means coupled to at least one of said plurality of registers for receiving signals corresponding to said operation code and for generating output signals indicative of the class of instruction to be processed in response to said operation code signals; and, hardware control decoder circuit means coupled to said cache unit for generating said cache command signals and signals for specifying said memory commands in accordance with said output signals from said means coupled to said one register, said hardware control decoder circuit means being conditioned by output signals from said means coupled to said one register indicating that an instruction stored in one of said plurality of registers is of a predetermined class to generate said cache command signals coded to specify a load quad buffer store operation together with said memory command signals and said cache unit further including: bypass detection means coupled to said directory, to said comparison means and to said processing unit, said bypass detection means generating an output signal upon detecting receipt of a predetermined number of sets of said cache command signals when said hit-miss detection signal indicates a miss condition, said output signal indicating that said processing unit is executing said predetermined class of instruction; and, said directory being inhibited by said output signal from storing second portions of the command addresses associated with predetermined ones of said predetermined number of sets of said cache command signals preventing a flushing of the contents of a substantial number of said plurality of locations of said buffer store with segments of data words fetched in response to said predetermined class of instruction.

Claim 31

A data processing system comprising: a main store including a plurality of word locations for storing data and instruction words; a cache unit operatively coupled to said main store for providing immediate access to said data and instruction words fetched from said main store in response to commands received from a processing unit including a command code and an address, said cache unit including: a buffer store including a plurality of addressable word locations arranged into a plurality of levels, each level containing a number of blocks of said word locations; an addressable directory having a plurality of locations corresponding in number to the number of levels in said buffer store, each location of said directory storing block addresses identifying the blocks of words within a corresponding one of said buffer store levels; comparison means coupled to said directory for comparing said block addresses read from said directory in response to said address of each of said commands and generating a hit-miss detection signal indicating whether or not the data word being requested is stored in said buffer store; and, said processing unit for processing instructions received from said main store, each instruction including an operation code, said processing unit being coupled to said cache unit for transferring and receiving information to and from said cache unit during the execution of said instructions, said processing unit including: control means for generating signals including cache command signals and said memory commands required for the execution of said instructions, said control means including: a plurality of registers for storing instructions received from said cache unit to be processed; means coupled to at least one of said plurality of registers for receiving signals corresponding to said operation code and for generating output signals indicative of the class of instruction to be processed in response to said operation code signals; and, hardware control decoder circuit means coupled to said cache unit for generating said cache command signals and signals for specifying said memory commands in accordance with said output signals from said means coupled to said one register, said hardware control decoder circuit means being conditioned by output signals from said means coupled to said one register indicating that an instruction stored in one of said plurality of registers is of a predetermined class to generate said cache command signals coded to specify a load quad buffer store operation together with said memory command signals and said cache unit further including: bypass detection means coupled to said directory, to said comparison means and to said processing unit, said bypass detection means generating an output signal upon detecting receipt of a predetermined number of sets of said cache command signals when said hit-miss detection signal indicates a miss condition, said output signal indicating that said processing unit is executing said predetermined class of instruction; and, said directory being inhibited by said output signal from storing second portions of the command addresses associated with predetermined ones of said predetermined number of sets of said cache command signals preventing a flushing of the contents of a substantial number of said plurality of locations of said buffer store with segments of data words fetched in response to said predetermined class of instruction.

Claim 32

The system of claim 28 wherein said bypass detection means comprises: decoder means coupled to said processing unit; indicator circuit means coupled to said decoder means, said indicator circuit means being switched from a first state to a second state by said decoder means in response to a predetermined one of said predetermined number of sets of said cache command signals; and, bistable control means coupled to said indicator means, to said decoder means and to said comparison means, said bistable control means being conditioned by said decoder means in response to another one of said predetermined number of sets of cache command signals when conditioned by said hit-miss detection signal indicative of a miss condition to switch from said first to said second state for generating said output signal.

Claim 33

The system of claim 28 wherein said predetermined number of said sets of said cache command signals represents replacement of the contents of a number of locations of said buffer store sufficient to accommodate short move operations.

Claim 34

The system of claim 28 wherein each instruction includes a number of addresses and wherein the number of sets of said cache command signals specifying load quad buffer operations varies in accordance with the number of data words defining a pair of data strings specified by first and second ones of said number of addresses to be operated upon as specified by said operation code.

Claim 35

The system of claim 31 wherein said operation code is coded to specify a move operation.

Claim 36

The system of claim 28 wherein each of said locations of said directory include a plurality of bit positions for storing level assignment signals identifying a next level within said buffer store into which a segment of data words fetched from said main store is to be placed; and, replacement circuit means for generating said level assignment signals in a predetermined pattern, said replacement circuit means being coupled to said directory and to said bypass detection means, said directory being conditioned by said output signal to prevent assigning the level specified by said level assignment signals.

Claim 37

The system of claim 28 wherein said cache unit further includes: an address register including a number of bit positions for storing an address of a next data word to be accessed by said processing unit; a data buffer coupled to said main store, said buffer comprising a plurality of addressable locations for storing a segment of data consisting of a number of data words, each location for storing a data word and an indicator signal for designating when said word has been stored therein; and, compare circuit means coupled to said address register and to said data buffer, said compare circuit means for enabling the transfer of requested data words to said processing unit upon detecting that the data word specified by the address contents of said address register has been received from said main store and is being written into one of said data buffer locations.

Claim 38

The system of claim 34 wherein said cache unit further includes: write flag indicator means coupled to said bypass detection means, said write flag indicator means for storing an indication specifying when a requested segment of data words is to be written into one of said buffer store levels; and, memory write control means coupled to said buffer store and to said write flag indicator means, said write control means for generating signals for enabling said segment of data words received from said main store to be written into said one level, said output signal from said detection means inhibiting said write flag indicator means for storing said indication for preventing said memory write control means from generating said signals for writing said segment into said buffer store level.

Claim 39

The system of claim 28 wherein said means coupled to said one register further includes microprogram control means including: an addressable address store coupled to receive signals corresponding to said operation code, said address store including a plurality of locations, each for storing a word including at least a first address identifying a first microinstruction of a different one of a plurality of execution sequences and an output register connected to said address store for storing the word contents of a location specified by said operation code; and, a cycled addressable control store including a plurality of locations storing at least one microinstruction of a different one of said plurality of execution sequences required for controlling the operation of said processing unit during the execution of said instructions and an output register connected to said control store, said control store output register for temporarily storing tthe microinstruction contents of an accessed location during a cycle of operation of said control store, one of said plurality of execution sequences including a number of microinstructions coded for conditioning said processing unit during execution of the operation specified by said operation code specifying said predetermined class of instruction, each of said microinstructions including a number of fields, at least one of said number of fields being used to specify cache commands and said hardware control decoder circuit means being coupled to said control store output register and to said address store output register, said hardware control decoder circuit means being operative in response to signals from said word contents of said location specified by said operation code and said one field of each microinstruction read out from said control store containing a predetermined code to generate said cache command signals coded for specifying said load quad operations.

Claim 40

The system of claim 36 wherein said microprogram control means further includes branch control means coupled to a number of indicator storage circuits and coupled to said control store for conditioning said control store to branch to microinstructions within said sequence in accordance with signals corresponding to the states of said indicator storage circuits and said branch control means in response to a signal from a predetermined one of said indicator storage circuits to condition said control store to branch to a location within said control store for terminating the execution of said instruction.

Claim 41

The system of claim 37 wherein said system further includes interface signalling means coupled to said predetermined one of said indicator storage circuits and to said indicator circuit means, said predetermined one of said indicator storage circuits when switched to said predetermined state conditioning said bypass detection circuit means for processing a next instruction.