Multiple register variably addressable semiconductor mass memory

Claim 2

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circuits as a common substrate, each of said basic circuits comprising: a bus portion including at least one signal line sharing address and data information, and a control signal line, said bus portion interconnecting said plurality of basic circuits; a plurality of first means for storing data signals; a plurality of second means each capable of storing a different address; means for enabling one of said plurality of second storage means to store a unique address transmitted over said shared signal line; means for controlling the transfer of data signals between said shared signal line and one of said first storage means; means responsive to a comparison between address signals received over said shared signal line and said stored address for actuating said controlling means; second means for connecting said shared signal line to said actuating means and to said plurality of first storage means; means for disabling said second connecting means to thereby disconnect said one basic circuit from said signal bus; and means responsive to the status of all other basic circuits and all other of said plurality of second storage means for alternatively inhibiting or actuating said enabling means, whereby one and only one of said second storage means is enabled to store a unique address at any given time.

Claim 3

An integrated-circuit store according to claim 1, wherein said second connecting means comprises one or more fuses.

Claim 4

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circuits as a common substrate, each of said basic circuits comprising: a bus portion including at least one address signal line, a data signal line, and a control signal line, said bus portion interconnecting said plurality of basic circuits; a plurality of first means for storing data signals; a plurality of second means each capable of storing a different address; means for enabling one of said plurality of second storage means to store a unique address transmitted over said at least one address signal line; means for controlling the transfer of data signals between said data signal line and one of said first storage means; means responsive to a comparison between address signals received over said at least one address signal line and said stored address for actuating said controlling means; second means for connecting said address signal line to said actuating means and for connecting said data signal line to said plurality of first storage means; means for disabling said second connecting means to thereby disconnect said one basic circuit from said signal bus; and means responsive to the status of all other basic circuits and all other of said plurality of second storage means for alternatively inhibitiNg or actuating said enabling means, whereby one and only one of said second storage means is enabled to store a unique address at any given time.

Claim 5

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circuits as a common substrate, each of said basic circuits comprising: a bus portion including at least one address signal line, a data signal line, and a control signal line, said bus portion interconnecting said plurality of basic circuits; a plurality of first means for storing data signals; a plurality of second means each capable of storing a different address; means for enabling one of said plurality of second storage means to store a unique address transmitted over said at least one address signal line; means for controlling the transfer of data signals between said data signal line and one of said first storage means; means responsive to a comparison between address signals received over said at least one address signal line and said stored address for actuating said controlling means; second means for connecting said address signal line to said actuating means and for connecting said data signal line to said plurality of first storage means; means for disabling said second connecting means to thereby disconnect said one basic circuit from said signal bus; and means responsive to the status of all other basic circuits and all other of said plurality of second storage means for alternatively inhibitiNg or actuating said enabling means, whereby one and only one of said second storage means is enabled to store a unique address at any given time.

Claim 6

An integrated-circuit store according to claim 3, wherein said second connecting means comprises one or more fuses.

Claim 7

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circuits as a common substrate, each of said basic circuits comprising: a bus portion including a shared signal line over which address and data-in signals may be transmitted, a control signal line, and a data-out line, said bus portion interconnecting said plurality of basic circuits; a plurality of first means for storing data signals; a plurality of second means each capable of storing a different address; means for enabling one of said plurality of second storage means to store a unique address transmitted over said shared signal line; means for controlling the transfer of data-in signals between said shared signal line and one of said first storage means; means responsive to a comparison between address signals received over said shared signal line and said stored address for actuating said controlling means; second means for connecting said shared signal line to said actuating means and to said plurality of first storage means; means for disabling said second connecting means to thereby disconnect said one basic circuit from said signal bus; third connecting means for connecting said plurality of first storage means to said data-out line; means for selectively disabling said third connecting means to thereby disconnect one or more of said plurality of first means from said data-out line; and means responsive to the status of all other basic circuits and all other of said plurality of second storage means for alternatively inhibiting or actuating said enabling means, whereby one and only one of said second storage means is enabled to store a unique address at any given time.

Claim 8

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circuits as a common substrate, each of said basic circuits comprising: a bus portion including a shared signal line over which address and data-in signals may be transmitted, a control signal line, and a data-out line, said bus portion interconnecting said plurality of basic circuits; a plurality of first means for storing data signals; a plurality of second means each capable of storing a different address; means for enabling one of said plurality of second storage means to store a unique address transmitted over said shared signal line; means for controlling the transfer of data-in signals between said shared signal line and one of said first storage means; means responsive to a comparison between address signals received over said shared signal line and said stored address for actuating said controlling means; second means for connecting said shared signal line to said actuating means and to said plurality of first storage means; means for disabling said second connecting means to thereby disconnect said one basic circuit from said signal bus; third connecting means for connecting said plurality of first storage means to said data-out line; means for selectively disabling said third connecting means to thereby disconnect one or more of said plurality of first means from said data-out line; and means responsive to the status of all other basic circuits and all other of said plurality of second storage means for alternatively inhibiting or actuating said enabling means, whereby one and only one of said second storage means is enabled to store a unique address at any given time.

Claim 9

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circuits as a common substrate, each of said basic circuits comprising: a bus portion including at least one shared signal line over which address and data-in signals may be transmitted, a control signal line, and a data-out line, said bus portion interconnecting said plurality of basic circuits; a plurality of shift registers for storing said data-in signals; a plurality of address registers each capable of storing a different address, each of said address registers being associated with a different one of said shift registers; means for enabling one of said plurality of address registers to store a unique address transmitted over said shared signal line; means for controlling the transfer of data-in signals between said shared signal line and one of said shift registers; means responsive to a comparison between address signals received over said shared signal line and said stored address for actuating said controlling means; second means for connecting said shared signal line to said actuating means and to said plurality of shift registers; means for disabling said second connecting means to thereby disconnect said one basic circuit from said signal bus; third means for connecting said shift registers to said data-out line; means for selectively disabling said third connecting means to thereby disconnect one or more of said shift registers from said data-out line; and means responsive to the status of all other basic circuits and all other of said plurality of address registers for alternatively inhibiting or actuating said enabling means, whereby one and only one of said address registers is enabled to store a unique address at any given time.

Claim 10

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circuits as a common substrate, each of said basic circuits comprising: a bus portion including at least one shared signal line over which address and data-in signals may be transmitted, a control signal line, and a data-out line, said bus portion interconnecting said plurality of basic circuits; a plurality of shift registers for storing said data-in signals; a plurality of address registers each capable of storing a different address, each of said address registers being associated with a different one of said shift registers; means for enabling one of said plurality of address registers to store a unique address transmitted over said shared signal line; means for controlling the transfer of data-in signals between said shared signal line and one of said shift registers; means responsive to a comparison between address signals received over said shared signal line and said stored address for actuating said controlling means; second means for connecting said shared signal line to said actuating means and to said plurality of shift registers; means for disabling said second connecting means to thereby disconnect said one basic circuit from said signal bus; third means for connecting said shift registers to said data-out line; means for selectively disabling said third connecting means to thereby disconnect one or more of said shift registers from said data-out line; and means responsive to the status of all other basic circuits and all other of said plurality of address registers for alternatively inhibiting or actuating said enabling means, whereby one and only one of said address registers is enabled to store a unique address at any given time.

Claim 11

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circUits as a common substrate, each of said basic circuits comprising: a bus portion including a shared signal line over which address and data-in signals may be transmitted, a data-out line, and a control signal line, said bus portion interconnecting said plurality of basic circuits; a plurality of first means for storing said data-in signals; a plurality of second means for storing different addresses; a plurality of third means connected to said control signal line each capable of storing at least one status signal, said plurality of first, second, and third storage means being so arranged that each of said first storage means has associated with it a unique one of said second and third storage means; means responsive to each of said third storage means for selectively enabling the second storage means associated with it to store a unique address transmitted over said shared signal line; means for controlling the transfer of data-in signals between said shared signal line and one of said plurality of first storage means; means responsive to a comparison between address signals received over said shared signal line and said stored address for actuating said controlling means; second means for connecting said shared signal line to said actuating means and to said plurality of first storage means, and for connecting said control signal line to said plurality of third storage means; means for disabling said second connecting means, thereby disconnecting said one basic circuit from said signal bus; third means for connecting said plurality of first storage means to said data-out line; and means for selectively disabling said third connecting means, thereby disconnecting one or more of said first storage means from said signal bus.

Claim 12

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circUits as a common substrate, each of said basic circuits comprising: a bus portion including a shared signal line over which address and data-in signals may be transmitted, a data-out line, and a control signal line, said bus portion interconnecting said plurality of basic circuits; a plurality of first means for storing said data-in signals; a plurality of second means for storing different addresses; a plurality of third means connected to said control signal line each capable of storing at least one status signal, said plurality of first, second, and third storage means being so arranged that each of said first storage means has associated with it a unique one of said second and third storage means; means responsive to each of said third storage means for selectively enabling the second storage means associated with it to store a unique address transmitted over said shared signal line; means for controlling the transfer of data-in signals between said shared signal line and one of said plurality of first storage means; means responsive to a comparison between address signals received over said shared signal line and said stored address for actuating said controlling means; second means for connecting said shared signal line to said actuating means and to said plurality of first storage means, and for connecting said control signal line to said plurality of third storage means; means for disabling said second connecting means, thereby disconnecting said one basic circuit from said signal bus; third means for connecting said plurality of first storage means to said data-out line; and means for selectively disabling said third connecting means, thereby disconnecting one or more of said first storage means from said signal bus.

Claim 13

The integrated-circuit store according to claim 7, in which each of said first storage means comprises a shift register, each of said plurality of second means comprises an address register, and each of said plurality of third means comprises a flip-flop.

Claim 14

The integrated-circuit store according to claim 8, wherein said second and third connecting means comprise fuses.

Claim 15

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circuits as a common substrate, each of said basic circuits comprising: a bus portion including at least one signal line shared by address and data-in information, a data-out line, and a control signal line, said bus portion interconnecting said plurality of basic circuits; a plurality of sub-circuits, each of said sub-circuits comprising: first means for storing data signals; second means for storing a unique address; third means connected to said control signal line for storing at least one status signal; means responsive to said third storage means for selectively enabling the second storage means to store a unique address transmitted over the shared signal line; means for controlling the transfer of data signals between said shared signal line and any one of the first storage means of said sub-circuits; means responsive to a comparison between address signals received over said shared signal line and said stored address for actuating said controlling means; second means for connecting said shared signal line to said actuating means, and for connecting said control signal line to the third storage means of said sub-circuits; means for disabling said second connecting means, thereby disconnecting said one basic circuit from said signal bus; third means for connecting each of said first storage means to said data-out line; and means for selectively disabling any of said third connecting means, thereby disconnecting one or more of said first storage means from said signal bus.

Claim 16

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circuits as a common substrate, each of said basic circuits comprising: a bus portion including at least one signal line shared by address and data-in information, a data-out line, and a control signal line, said bus portion interconnecting said plurality of basic circuits; a plurality of sub-circuits, each of said sub-circuits comprising: first means for storing data signals; second means for storing a unique address; third means connected to said control signal line for storing at least one status signal; means responsive to said third storage means for selectively enabling the second storage means to store a unique address transmitted over the shared signal line; means for controlling the transfer of data signals between said shared signal line and any one of the first storage means of said sub-circuits; means responsive to a comparison between address signals received over said shared signal line and said stored address for actuating said controlling means; second means for connecting said shared signal line to said actuating means, and for connecting said control signal line to the third storage means of said sub-circuits; means for disabling said second connecting means, thereby disconnecting said one basic circuit from said signal bus; third means for connecting each of said first storage means to said data-out line; and means for selectively disabling any of said third connecting means, thereby disconnecting one or more of said first storage means from said signal bus.

Claim 17

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circuits as a common substrate, eacH of said basic circuits comprising: a bus portion including at least one address signal line, a data-in line, a data-out line, and a control signal line, said bus portion interconnecting said plurality of basic circuits; a plurality of first means for storing data signals; a plurality of second means each capable of storing a different address; means for enabling one of said plurality of second storage means to store a unique address transmitted over said at least one address signal line; means for controlling the transfer of data signals between said data-in line and one of said first storage means; means responsive to a comparison between address signals received over said at least one address signal line and said stored address for actuating said controlling means; second means for connecting said at least one address signal line to said actuating means, and for connecting said data-in line to said first storage means; third means for connecting said data-out line to said first storage means; means for disabling said second connecting means to thereby disconnect said one basic circuit from said signal bus; means for selectively disabling said third connecting means to thereby disconnect one or more of said first storage means from said signal bus; and means responsive to the status of all other basic circuits and all other of said plurality of second storage means for alternatively inhibiting or actuating said enabling means, whreby one and only one of said second storage means is enabled to store a unique address at any given time.

Claim 18

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circuits as a common substrate, eacH of said basic circuits comprising: a bus portion including at least one address signal line, a data-in line, a data-out line, and a control signal line, said bus portion interconnecting said plurality of basic circuits; a plurality of first means for storing data signals; a plurality of second means each capable of storing a different address; means for enabling one of said plurality of second storage means to store a unique address transmitted over said at least one address signal line; means for controlling the transfer of data signals between said data-in line and one of said first storage means; means responsive to a comparison between address signals received over said at least one address signal line and said stored address for actuating said controlling means; second means for connecting said at least one address signal line to said actuating means, and for connecting said data-in line to said first storage means; third means for connecting said data-out line to said first storage means; means for disabling said second connecting means to thereby disconnect said one basic circuit from said signal bus; means for selectively disabling said third connecting means to thereby disconnect one or more of said first storage means from said signal bus; and means responsive to the status of all other basic circuits and all other of said plurality of second storage means for alternatively inhibiting or actuating said enabling means, whreby one and only one of said second storage means is enabled to store a unique address at any given time.

Claim 19

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circuits as a common substrate, each of said basic circuits comprising: a bus portion including at least one address signal line, a data-in line, a data-out line, and a control signal line, said bus portion interconnecting said plurality of basic circuits; a plurality of first means for storing data signals; a plurality of second means for storing different addresses; a plurality of third means connected to said control signal line each capable of storing at least one status signal, said plurality of first, second, and third storage means being so arranged that each of said first storage means has associated with it a unique one of said second and third storage means; means responsive to each of said third storage means for selectively enabling the second storage means associated with it to store a unique address transmitted over said address signal line; means for controlling the transfer of data signals between said data-in line and said plurality of first storage means; means responsive to a comparison between address signals received over said at least one address signal line and one of said stored addresses for actuating said controlling means; second means for connecting said at least one address signal line means to said actuating means, for connecting said data-in line to said plurality of first storage means, and for connecting said control signal line to said plurality of third storage means; means for disabling said second connecting means, thereby disconnecting said one basic circuit from said signal bus; third means for connecting said plurality of first storage means to said data-out line; and means for selectively disabling said third connecting means, thereby disconnecting one or more of said first storage means from said signal bus.

Claim 20

An integrated-circuit store comprising a body of semiconductor material having formed thereon a plurality of basic circuits as a common substrate, each of said basic circuits comprising: a bus portion including at least one address signal line, a data-in line, a data-out line, and a control signal line, said bus portion interconnecting said plurality of basic circuits; a plurality of first means for storing data signals; a plurality of second means for storing different addresses; a plurality of third means connected to said control signal line each capable of storing at least one status signal, said plurality of first, second, and third storage means being so arranged that each of said first storage means has associated with it a unique one of said second and third storage means; means responsive to each of said third storage means for selectively enabling the second storage means associated with it to store a unique address transmitted over said address signal line; means for controlling the transfer of data signals between said data-in line and said plurality of first storage means; means responsive to a comparison between address signals received over said at least one address signal line and one of said stored addresses for actuating said controlling means; second means for connecting said at least one address signal line means to said actuating means, for connecting said data-in line to said plurality of first storage means, and for connecting said control signal line to said plurality of third storage means; means for disabling said second connecting means, thereby disconnecting said one basic circuit from said signal bus; third means for connecting said plurality of first storage means to said data-out line; and means for selectively disabling said third connecting means, thereby disconnecting one or more of said first storage means from said signal bus.

Claim 21

An integrated-circuit store having connected thereto from an external source means for transmitting address signals, means for transmitting data signals, and means for transmitting at least one control signal and adapted to receive address and control signals from said external source and to transfer data signals to and from said external source, said store comprising a body of semiconductor material, a plurality of basic circuits formed on said body of seMiconductor material as a common substrate, and means for connecting said transmitting means to at least one of said plurality of basic circuits, each one of said basic circuits comprising: a bus portion including at least one address signal line, a data signal line, and a control signal line, said bus portion interconnecting said plurality of basic circuits; a plurality of first means for storing data signals; a plurality of second means for storing different addresses; a plurality of third means connected to said control signal line each capable of storing at least one status signal, said plurality of first, second, and third storage means being so arranged that each of said first storage means has associated with it a unique one of said second and third storage means; means responsive to each of said third storage means for selectively enabling the second storage means associated with it to store a unique address transmitted over said address signal line; means for controlling the transfer of data signals between said data signal line and one of said plurality of first storage means; means responsive to a comparison between address signals received over said at least one address signal line and said stored address for actuating said controlling means; second means for connecting said at least one address signal line means to said actuating means, for connecting said data signal line to said plurality of first storage means, and for connecting said control signal line to said plurality of third storage means; and means for disabling said second connecting means, thereby disconnecting said one basic circuit from said signal bus.

Claim 22

An integrated-circuit store having connected thereto from an external source means for transmitting address signals, means for transmitting data signals, and means for transmitting at least one control signal and adapted to receive address and control signals from said external source and to transfer data signals to and from said external source, said store comprising a body of semiconductor material, a plurality of basic circuits formed on said body of seMiconductor material as a common substrate, and means for connecting said transmitting means to at least one of said plurality of basic circuits, each one of said basic circuits comprising: a bus portion including at least one address signal line, a data signal line, and a control signal line, said bus portion interconnecting said plurality of basic circuits; a plurality of first means for storing data signals; a plurality of second means for storing different addresses; a plurality of third means connected to said control signal line each capable of storing at least one status signal, said plurality of first, second, and third storage means being so arranged that each of said first storage means has associated with it a unique one of said second and third storage means; means responsive to each of said third storage means for selectively enabling the second storage means associated with it to store a unique address transmitted over said address signal line; means for controlling the transfer of data signals between said data signal line and one of said plurality of first storage means; means responsive to a comparison between address signals received over said at least one address signal line and said stored address for actuating said controlling means; second means for connecting said at least one address signal line means to said actuating means, for connecting said data signal line to said plurality of first storage means, and for connecting said control signal line to said plurality of third storage means; and means for disabling said second connecting means, thereby disconnecting said one basic circuit from said signal bus.

Claim 23

An integrated-circuit store according to claim 13 further comprising: means for selectively transmitting said at least one status signal stored within one of said plurality of third means over said control signal line to the remainder of said basic circuits and to predetermined others of said third means within said one basic circuit; and means associated with said integrated circuit store for enabling one and only one of said third means of said basic circuits to be responsive to said transmitted status signal at any given time, whereby a unique address may be assigned to each of said plurality of second storage means.

Claim 24

An integrated-circuit store having applied thereto from a controller a plurality of address and control signals and connected to an external data line and adapted to transfer data signals to and from said external data line, said store comprising a body of semiconductor material, and a plurality of basic circuits formed on said body of semiconductor material as a common substrate, each one of said basic circuits comprising: a bus portion including one or more address signal lines, one or more control signal lines, and a data signal line, said bus portion abutting a like adjacent bus portion to form therewith a signal bus interconnecting said plurality of basic circuits; switching means; a plurality of first means for storing data signals; a plurality of second means each capable of storing a different address; a plurality of third means each capable of storing a status signal, said plurality of first, second, and third storage means being so arranged that each of said first storage means has associated with it a unique one of said second and third storage means; enabling means associated with each of said third means and responsive to said status signal for selectively enabling the associated second storage means to store a unique address transmitted over said one or more address signal lines; fourth means associated with each of said third means for selectively inhibiting the operation of said enabling means, said fourth means being responsive to the contents of said third means, to the contents of predetermined others of said third means within said one basic circuit, and to an inhibit control signal transmitted over said One or more control signal lines; fifth means, associated with said one or more control signal lines, for ordering said one basic circuit relative to the other basic circuits of said integrated-circuit store, said fifth means being responsive to the contents of all of said third means of the basic circuits of higher order than said one basic circuit to selectively generate said inhibit control signal over said one or more control signal lines to the basic circuits of lower order; sixth means, also associated with said one or more control signal lines, for ordering said second storage means relative to one another, said sixth storage means being responsive to the contents of all of said third means within said one basic circuit to selectively transmit said inhibit control signal to predetermined ones of said fourth means within said one basic circuit; means for comparing address signals transmitted over said one or more address signal lines with the contents of said second storage means, said comparing means being responsive to a concidence between said address signals and a stored address within a particular second storage means to generate a control enable signal; seventh means connected to each of said plurality of first storage means and responsive to said control enable signal to control the transfer of said data signals between said data signal line and the first storage means associated with said particular second storage means; second means for connecting via said switching means said address signals to said comparing means, said control signals to said fourth, fifth and sixth means, and said data signal line to said seventh means and said first storage means; and means for selectively disabling said switching means to disconnect alternatively said one basic circuit or one or more of said first storage means from said signal bus.

Claim 25

An integrated-circuit store having applied thereto from a controller a plurality of address and control signals and connected to an external data line and adapted to transfer data signals to and from said external data line, said store comprising a body of semiconductor material, and a plurality of basic circuits formed on said body of semiconductor material as a common substrate, each one of said basic circuits comprising: a bus portion including one or more address signal lines, one or more control signal lines, and a data signal line, said bus portion abutting a like adjacent bus portion to form therewith a signal bus interconnecting said plurality of basic circuits; switching means; a plurality of first means for storing data signals; a plurality of second means each capable of storing a different address; a plurality of third means each capable of storing a status signal, said plurality of first, second, and third storage means being so arranged that each of said first storage means has associated with it a unique one of said second and third storage means; enabling means associated with each of said third means and responsive to said status signal for selectively enabling the associated second storage means to store a unique address transmitted over said one or more address signal lines; fourth means associated with each of said third means for selectively inhibiting the operation of said enabling means, said fourth means being responsive to the contents of said third means, to the contents of predetermined others of said third means within said one basic circuit, and to an inhibit control signal transmitted over said One or more control signal lines; fifth means, associated with said one or more control signal lines, for ordering said one basic circuit relative to the other basic circuits of said integrated-circuit store, said fifth means being responsive to the contents of all of said third means of the basic circuits of higher order than said one basic circuit to selectively generate said inhibit control signal over said one or more control signal lines to the basic circuits of lower order; sixth means, also associated with said one or more control signal lines, for ordering said second storage means relative to one another, said sixth storage means being responsive to the contents of all of said third means within said one basic circuit to selectively transmit said inhibit control signal to predetermined ones of said fourth means within said one basic circuit; means for comparing address signals transmitted over said one or more address signal lines with the contents of said second storage means, said comparing means being responsive to a concidence between said address signals and a stored address within a particular second storage means to generate a control enable signal; seventh means connected to each of said plurality of first storage means and responsive to said control enable signal to control the transfer of said data signals between said data signal line and the first storage means associated with said particular second storage means; second means for connecting via said switching means said address signals to said comparing means, said control signals to said fourth, fifth and sixth means, and said data signal line to said seventh means and said first storage means; and means for selectively disabling said switching means to disconnect alternatively said one basic circuit or one or more of said first storage means from said signal bus.

Claim 26

An integrated-circuit store according to claim 15, wherein said second connecting means comprises one or more fuses.

Claim 27

An integrated-circuit store having applied thereto from a controller a plurality of address and control signals and connected to an external data line and adapted to transfer data signals to and from said external data line, said store comprising a body of semiconductor material, and a plurality of basic circuits formed on said body of semiconductor material as a common substrate, each one of said basic circuits comprising: a bus portion including a plurality of address, control, and data signal lines, said bus portion abutting a like adjacent bus portion to form therewith a signal bus interconnecting said plurality of basic circuits; a first switching means; a set of second switching means; a plurality of first means for storing data signals; a plurality of second means each capable of storing a different address; a plurality of third means each capable of storing a status signal, said plurality of first, second, and third storage means being so arranged that each of said first storage means has associated with it a unique one of said second and third storage means; enabling means associated with each of said third means and responsive to said status signal for selectively enabling the associated second storage means to store a unique address transmitted over said address signal lines; fourth means associated with each of said third means for selectively inhibiting the operation of said enabling means, said fourth means being responsive to the contents of said third means, to the contents of predetermined others of said third means within said one basic circuit, and to an inhibit control signal transmitted over a predetermined one of said control signal lines; fifth means, associated with said predetermined control signal line, for ordering said one basic circuit relative to the other basic circuits of said integrated-circuit store, said fifth means being responsive to the contents of all of said third means of the basic circuits of higher order than said one basic circuit to selectively generate said inhibit control signal over said predetermined control signal line to the basic circuits of lower order; sixth means, associated with said predetermined control signal line, for ordering said second storage means within said one basic circuit relative to one another, said sixth storage means being responsive to the contents of all of said third means within said one basic circuit to selectively transmit said inhibit control signal to predetermined ones of said fourth means within said one basic circuit; means for comparing address signals transmitted over said address signal lines with the contents of said second storage means, said comparing means being responsive to a coincidence between said address signals and a stored address within a particular second storage means to generate a control enable signal; seventh means connected to each of said plurality of first storage means and responsive to said control enable signal to control the transfer of said data signals between one of said data signal lines and the first storage means associated with said particular second storage means; second means for connecting via said first switching means said address signals to said comparing means, said control signals to said fourth, fifth and sixth means, and said one data signal line to said seventh means; means for disabling said first switching means, thereby disconnecting said one basic circuit from said signal bus; third means for connecting via said set of second switching means another of said data lines with said plurality of first storage means; and means for disabling any of said second switching means, thereby disconnecting one or more of said first storage means from said signal bus.

Claim 28

An integrated-circuit store having applied thereto from a controller a plurality of address and control signals and connected to an external data line and adapted to transfer data signals to and from said external data line, said store comprising a body of semiconductor material, and a plurality of basic circuits formed on said body of semiconductor material as a common substrate, each one of said basic circuits comprising: a bus portion including a plurality of address, control, and data signal lines, said bus portion abutting a like adjacent bus portion to form therewith a signal bus interconnecting said plurality of basic circuits; a first switching means; a set of second switching means; a plurality of first means for storing data signals; a plurality of second means each capable of storing a different address; a plurality of third means each capable of storing a status signal, said plurality of first, second, and third storage means being so arranged that each of said first storage means has associated with it a unique one of said second and third storage means; enabling means associated with each of said third means and responsive to said status signal for selectively enabling the associated second storage means to store a unique address transmitted over said address signal lines; fourth means associated with each of said third means for selectively inhibiting the operation of said enabling means, said fourth means being responsive to the contents of said third means, to the contents of predetermined others of said third means within said one basic circuit, and to an inhibit control signal transmitted over a predetermined one of said control signal lines; fifth means, associated with said predetermined control signal line, for ordering said one basic circuit relative to the other basic circuits of said integrated-circuit store, said fifth means being responsive to the contents of all of said third means of the basic circuits of higher order than said one basic circuit to selectively generate said inhibit control signal over said predetermined control signal line to the basic circuits of lower order; sixth means, associated with said predetermined control signal line, for ordering said second storage means within said one basic circuit relative to one another, said sixth storage means being responsive to the contents of all of said third means within said one basic circuit to selectively transmit said inhibit control signal to predetermined ones of said fourth means within said one basic circuit; means for comparing address signals transmitted over said address signal lines with the contents of said second storage means, said comparing means being responsive to a coincidence between said address signals and a stored address within a particular second storage means to generate a control enable signal; seventh means connected to each of said plurality of first storage means and responsive to said control enable signal to control the transfer of said data signals between one of said data signal lines and the first storage means associated with said particular second storage means; second means for connecting via said first switching means said address signals to said comparing means, said control signals to said fourth, fifth and sixth means, and said one data signal line to said seventh means; means for disabling said first switching means, thereby disconnecting said one basic circuit from said signal bus; third means for connecting via said set of second switching means another of said data lines with said plurality of first storage means; and means for disabling any of said second switching means, thereby disconnecting one or more of said first storage means from said signal bus.

Claim 29

An integrated-circuit store according to claim 17 wherein said first and second switching means comprises one or more fuses.

Claim 30

An integrated-circuit store according to claim 17 wherein said first and second switching means comprises one or more semipermanent voltage-programmable transistors.

Claim 31

An integrated-circuit store according to claim 17 wherein said first and second switching means comprises one or more programmable connective devices.