Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines

Claim 2

An interface for interfacing VLSI CMOS binary circuits to a terminated transmission line for binary communications between said circuits at signal levels providing a signal swing of about 0.8 v-1.4 v between a line terminating voltage level of about 1.2 v-2.0 v and a low voltage level of about 0.4 v-0.6 v; said interface comprising driver means for feeding binary signals from said CMOS circuits to said transmission line; each of said driver means including an N-channel transistor means having a drain coupled to said transmission line, a source returned to ground, and a gate coupled to receive binary signals from one of said CMOS circuits; the gate of said transistor means being of predetermined effective width and length, with its width being plural orders of magnitude greater than its length.

Claim 3

The interface of claim 1 further comprising receiver means for feeding binary signals from said transmission line to said CMOS circuits, each of said receiver means including a N-channel transistor, a P-channel transistor, a reference means for supplying a predetermined reference voltage, and a bias means for supplying a predetermined bias voltage; said N-channel transistor having a source coupled to said transmission line, a drain, and a gate coupled to said reference means; said P-channel transistor having a source coupled to a power supply, a drain coupled to the drain of said N-channel transistor, and a gate coupled to said bias means; said bias voltage being selected to bias said P-channel transistor for conduction; and said reference voltage being selected for switching said N-channel transistor into and out of conduction as the signal on said transmission line drops below and rises above, respectively, a predetermined decision threshold near dead center of said signal swing.

Claim 4

The interface of claim 2 wherein each of said receiver means further includes amplifier means coupled to the drains of said transistors; and a flip-flop coupled to said amplifier means, said flip-flop being prepared to switch from one state to another when the signal on said transmission line drops below and rises above, respectively, said decision threshold by a predetermined amount.

Claim 5

An interface for interfacing VLSI CMOS binary circuits to a terminated transmission line for binary communications between said circuits at signal levels providing a nominal signal swing of up to about 1.4 v between a line terminating voltage level of up to about 2.0 v and a lower voltage level; said interface comprising driver means for feeding binary signals from said CMOS circuits to said transmission line; each of said driver means including an N-channel transistor means having a drain coupled to said transmission line, a source returned to ground, and a gate coupled to receive binary signals from one of said CMOS circuits; the gate of said transistor means being of predetermined effective width and length, with its width being plural orders of magnitude greater than its length.

Claim 6

An interface for interfacing VLSI CMOS binary circuits to a terminated transmission line for binary communications between said circuits at signal levels providing a nominal signal swing of up to about 1.4 v between a line terminating voltage level of up to about 2.0 v and a lower voltage level; said interface comprising driver means for feeding binary signals from said CMOS circuits to said transmission line; each of said driver means including an N-channel transistor means having a drain coupled to said transmission line, a source returned to ground, and a gate coupled to receive binary signals from one of said CMOS circuits; the gate of said transistor means being of predetermined effective width and length, with its width being plural orders of magnitude greater than its length.

Claim 7

The interface of any of claims 1, 2, 3 or 4 wherein said driver means further includes: a normally disabled switch means coupled between the source and gate of said N-channel transistor means; and means for enabling said switch means temporarily whenever said transistor means is being switched from a conductive state to a non-conductive state, thereby providing a negative feedback path from the source to the gate of said transistor means for a sufficient period of time to substantially damp switching transients at the source and drain of said transistor means.