US5473575A
Expired / Lapsed
US
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Integrated circuit I/O using a high performance bus interface
Assignee: Rambus Inc
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Filing: 1992-03-05
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Granted: 1995-12-05
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Expires: 2012-03-05
Abstract
Abstract The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and also bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.
Inventors
- 👤 Michael Farmwald
- 👤 Mark Horowitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:30
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G06; G06F; G06F11/00; G06F11/006; G06F12/00; G06F12/02; G06F12/0215; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F12/0684; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1668; G06F13/1678; G06F13/1689; G06F13/1694; G06F13/36; G06F13/368; G06F13/376; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4096; G11C29/00; G11C29/70; G11C29/88; G11C5/00; G11C5/02; G11C5/04; G11C5/06; G11C5/063; G11C5/066; G11C7/1006; G11C7/1012; G11C7/1015; G11C7/1045; G11C7/1057; G11C7/1069; G11C7/1072; G11C7/1078; G11C7/1084; G11C7/22; G11C7/222; G11C7/225; G11C8/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G11C2207/00; G11C2207/10; G11C2207/105; G11C2207/108; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
165 words
A complementary metal oxide semiconductor (CMOS) dynamic random access memory (DRAM) coupled to a multiline bus, wherein a first line of the multiline bus is a terminated transmission line, the CMOS DRAM comprising: (A) a CMOS memory array; (B) a driver for producing a low voltage swing signal on the first line of the multiline bus, wherein the low voltage swing signal swings between an upper voltage and a lower voltage, wherein the difference between the upper voltage and the lower voltage is less than one volt, wherein the driver comprises an N channel metal oxide semiconductor (NMOS) transistor having a first end, a second end, and a gate, wherein the first end of the NMOS transistor is coupled to ground, wherein the second end of the NMOS transistor is coupled to the first line of the multiline bus, wherein the first line of the multiline bus has a more positive voltage then ground, and wherein the gate is coupled to the CMOS memory array.
Claim 2
Dependent Claim
165 words
A complementary metal oxide semiconductor (CMOS) dynamic random access memory (DRAM) coupled to a multiline bus, wherein a first line of the multiline bus is a terminated transmission line, the CMOS DRAM comprising: (A) a CMOS memory array; (B) a driver for producing a low voltage swing signal on the first line of the multiline bus, wherein the low voltage swing signal swings between an upper voltage and a lower voltage, wherein the difference between the upper voltage and the lower voltage is less than one volt, wherein the driver comprises an N channel metal oxide semiconductor (NMOS) transistor having a first end, a second end, and a gate, wherein the first end of the NMOS transistor is coupled to ground, wherein the second end of the NMOS transistor is coupled to the first line of the multiline bus, wherein the first line of the multiline bus has a more positive voltage then ground, and wherein the gate is coupled to the CMOS memory array.
Claim 3
Dependent Claim
14 words
The CMOS DRAM of claim 1, wherein the driver is a current mode driver.
Claim 4
Dependent Claim
28 words
The CMOS DRAM of claim 1, wherein the upper voltage is set by a voltage on a termination resistor coupled to the first line of the multiline bus.
Claim 5
Dependent Claim
14 words
The CMOS DRAM of claim 1, wherein the upper voltage is approximately two volts.
Claim 6
Dependent Claim
30 words
The CMOS DRAM of claim 1, wherein a reference voltage is supplied to the CMOS DRAM and wherein the reference voltage is between the upper voltage and the lower voltage.
Claim 7
Dependent Claim
46 words
The apparatus of claim 1, wherein the CMOS DRAM further comprises: (A) two CMOS input receivers coupled to the first line of the multiline bus; (B) selection means for maximizing bandwidth by selecting the two CMOS input receivers alternately to sense the low voltage swing signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-04 | 1999-06-05 | 1999-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-04 | 2003-06-05 | 2003-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-04 | 2007-06-05 | 2007-12-05 | $7700.00 | Window Closed / Lapsed |