CMOS circuit with reduced signal swing

Claim 2

A semiconductor integrated circuit including a plurality of CMOS integrated circuit blocks, each of said plurality of CMOS integrated circuit blocks comprising: an input signal receiver unit for receiving an input signal having a first signal swing of a relatively small magnitude to convert it into an output signal having a second signal swing of a magnitude larger than that of said first signal swing; a signal processing unit for processing said output signal having said second signal swing, from said input signal receiver, to generate an output signal having said second signal swing; and an output driving unit for receiving said output signal having said second signal swing from said signal processing unit to convert it into an output having said first signal swing of said relatively small magnitude, wherein, in accordance with a given polarity direction, a high level of said second signal swing is higher in amplitude than that of said first signal swing, and a low level of said second signal swing is lower in amplitude than that of said first signal swing.

Claim 3

A semiconductor integrated circuit according to claim 1, wherein the magnitude of said first signal swing is less than 1 V.

Claim 4

A semiconductor integrated circuit according to claim 2, wherein the magnitude of said first signal swing is equal to the potential difference between the maximum value and the minimum value defined by a supply voltage supplied to the CMOS integrated circuit block.

Claim 5

A semiconductor integrated circuit according to claim 2, wherein the magnitude of said second signal swing is equal to the potential difference between the maximum value and the minimum value defined by a supply voltage supplied to the CMOS integrated circuit block.

Claim 6

A semiconductor integrated circuit according to claim 1, wherein said input signal receiver unit comprises: a first signal level conversion circuit having an input for receiving said input signal of said first signal swing at an input of said input signal receiver unit and having a first output node; a second signal level conversion circuit having an input for receiving said input signal of said first signal swing at the input of said input signal receiver unit and having a second output node; a first MOS transistor, of a first conductivity type, having a source connected to a first operating potential, a gate connected to said first output node of said first signal level conversion circuit and a drain connected to the output of said input signal receiver unit; and a second MOS transistor, of a second conductivity type opposite to said first conductivity type, having a source connected to a second operating potential, a gate connected to said second output node of said second signal level conversion circuit and a drain connected to the output of said input signal receiver unit.

Claim 7

A semiconductor integrated circuit according to claim 5, wherein said first signal level conversion circuit comprises: a third MOS transistor, of said first conductivity type, having a source connected to said first operating potential, a gate connected to said output of said input signal receiver unit and a drain connected to said first output node; and a fourth MOS transistor, of said second conductivity type, having a source connected to said input of said input signal receiver unit and a drain connected to said first output node, and wherein said second signal level conversion circuit comprises: a fifth MOS transistor, of said second conductivity type, having a source connected to said second operating potential, a gate connected to said output of said input a signal receiver unit and a drain connected to said second output node; and a sixth MOS transistor, of said first conductivity type, having a source connected to said input of said input signal receiver unit and a drain connected to said second output node.

Claim 8

A semiconductor integrated circuit according to claim 6, wherein a current flowing between said first operating potential and said second operating potential through respective source-drain paths of said first and second MOS transistors is a negligible value, when said input signal at the input of said input signal receiver unit is equal to a high level or a low level of said first signal swing.

Claim 9

A semiconductor integrated circuit according to claim 6, wherein said output driving unit comprises: a seventh MOS transistor, of said first conductivity type, having a source connected to a third operating potential, a gate connected to the input of said output driving unit and a drain connected to the output of said output driving unit; and an eighth MOS transistor, of said second conductivity type, having a source connected to a fourth operating potential, a gate connected to the input of said output driving unit and a drain connected to the output of said output driving unit.

Claim 10

A semiconductor integrated circuit according to claim 8, wherein absolute values of gate threshold voltages of said seventh and eighth MOS transistors are smaller than those of other MOS transistors included in said CMOS integrated circuit block.

Claim 11

A semiconductor integrated circuit according to claim 5, wherein a current flowing between said first operating potential and said second operating potential through respective source-drain paths of said first and second MOS transistors is a negligible value, when said input signal at the input of said input signal receiver unit is equal to a high level or a low level of said first signal swing.

Claim 12

A semiconductor integrated circuit according to claim 5, wherein said output driving unit comprises: a third MOS transistor, of said first conductivity type, having a source connected to a third operating potential, a gate connected to the input of said output driving unit and a drain connected to the output of said output driving unit; and a fourth MOS transistor, of said second conductivity type, having a source connected to a fourth operating potential, a gate connected to the input of said output driving unit and a drain connected to the output of said output driving unit.

Claim 13

A semiconductor integrated circuit according to claim 11, wherein absolute values of gate threshold voltages of said third and fourth MOS transistors are smaller than those of other MOS transistors included in said CMOS integrated circuit block.

Claim 14

A semiconductor integrated circuit according to claim 1, wherein said output driving unit comprises: a first MOS transistor, of a first conductivity type, having a source connected to a first operating potential, a gate connected to the input of said output driving unit and a drain connected to the output of said output driving unit; and a second MOS transistor, of a second conductivity type, opposite to said first conductivity type, having a source connected to a second operating potential, a gate connected to the input of said output driving unit and a drain connected to the output of said output driving unit.

Claim 15

A semiconductor integrated circuit according to claim 13, wherein absolute values of age threshold voltages of said first and second MOS transistors are smaller than those of other MOS transistors included in said CMOS integrated circuit block.

Claim 16

A semiconductor apparatus including a plurality of CMOS integrated circuits, each of said plurality of CMOS integrated circuits comprising: an input signal receiver unit for receiving an input signal having a first signal swing of a relatively small magnitude to convert it into an output signal having a second signal swing of a magnitude larger than that of said first signal swing; a signal processing unit for processing said output signal having said second signal swing, from said input signal receiver, to generate an output signal having said second signal swing; and an output driving unit for receiving said output signal having said second signal swing from said signal processing unit to convert it into an output having said first signal swing of said relatively small magnitude, wherein, in accordance with a given polarity direction, a high level of said second signal swing is higher in amplitude than that of said first signal swing, and a low level of said second signal swing is lower in amplitude than that of said first signal swing.

Claim 17

A semiconductor apparatus including a plurality of CMOS integrated circuits, each of said plurality of CMOS integrated circuits comprising: an input signal receiver unit for receiving an input signal having a first signal swing of a relatively small magnitude to convert it into an output signal having a second signal swing of a magnitude larger than that of said first signal swing; a signal processing unit for processing said output signal having said second signal swing, from said input signal receiver, to generate an output signal having said second signal swing; and an output driving unit for receiving said output signal having said second signal swing from said signal processing unit to convert it into an output having said first signal swing of said relatively small magnitude, wherein, in accordance with a given polarity direction, a high level of said second signal swing is higher in amplitude than that of said first signal swing, and a low level of said second signal swing is lower in amplitude than that of said first signal swing.

Claim 18

A semiconductor apparatus according to claim 15, wherein the magnitude of said first signal swing is less than 1 V.

Claim 19

A semiconductor apparatus according to claim 16, wherein the magnitude of said first signal swing is equal to the potential difference between the maximum value and the minimum value defined by a supply voltage supplied to the CMOS integrated circuit.

Claim 20

A semiconductor apparatus according to claim 16, wherein the magnitude of said second signal swing is equal to the potential difference between the maximum value and the minimum value defined by a supply voltage supplied to the CMOS integrated circuit.

Claim 21

A semiconductor apparatus according to claim 15, wherein said input signal receiver unit comprises: a first signal level conversion circuit having an input for receiving said input signal of said first signal swing at an input of said input signal receiver unit and having a first output node; a second signal level conversion circuit having an input for receiving said input signal of said first signal swing at the input of said input signal receiver unit and having a second output node; a first MOS transistor, of a first conductivity type, having a source connected to a first operating potential, a gate connected to said first output node of said first signal level conversion circuit and a drain connected to the output of said input signal receiver unit; and a second MOS transistor, of a second conductivity type opposite to said first conductivity type, having a source connected to a second operating potential, a gate connected to said second output node of said second signal level conversion circuit and a drain connected to the output of said input signal receiver unit.

Claim 22

A semiconductor apparatus according to claim 19, wherein said first signal level conversion circuit comprises: a third MOS transistor, of said first conductivity type, having a source connected to said first operating potential, a gate connected to said output of said input signal receiver unit and a drain connected to said first output node; and a fourth MOS transistor, of said second conductivity type, having a source connected to said input of said input signal receiver unit and a drain connected to said first output node, and wherein said second signal level conversion circuit comprises: a fifth MOS transistor, of said second conductivity type, having a source connected to said second operating potential, a gate connected to said output of said input a signal receiver unit and a drain connected to said second output node; and a sixth MOS transistor, of said first conductivity type, having a source connected to said input of said input signal receiver unit and a drain connected to said second output node.

Claim 23

A semiconductor apparatus according to claim 20, wherein a current flowing between said first operating potential and said second operating potential through respective source-drain paths of said first and second MOS transistors if s negligible value, when said input signal at the input of said input signal receiver unit is equal to a high level or a low level of said first signal swing.

Claim 24

A semiconductor apparatus according to claim 20, wherein said output driving unit comprises: a seventh MOS transistor, of said first conductivity type, having a source connected to a third operating potential, a gate connected to the input of said output driving unit and a drain connected to the output of said output driving unit; and an eighth MOS transistor, of said second conductivity type, having a source connected to a fourth operating potential, a gate connected to the input of said output driving unit and a drain connected to the output of said output driving unit.

Claim 25

A semiconductor apparatus according to claim 22, wherein absolute value of gate threshold voltages of said seventh and eighth MOS transistors are smaller than those of other MOS transistors included in said CMOS integrated circuit.

Claim 26

A semiconductor apparatus according to claim 19, wherein a current flowing between said first operating potential and said second operating potential through respective source-drain paths of said first and second MOS transistors is a negligible value, when said input signal at the input of said input signal receiver unit is equal to a high level or a low level of said first signal swing.

Claim 27

A semiconductor apparatus according to claim 19, wherein said output driving unit comprises: a third MOS transistor, of said first conductivity type, having a source connected to a third operating potential, a gate connected to the input of said output driving unit and a drain connected to the output of said output driving unit; and an fourth MOS transistor, of said second conductivity type, having a source connected to a fourth operating potential, a gate connected to the input of said output driving unit and a drain connected to the output of said output driving unit.

Claim 28

A semiconductor apparatus according to claim 25, wherein absolute values of gate threshold voltages of sad third and fourth MOS transistors are smaller than those of other MOS transistors included in said CMOS integrated circuit.

Claim 29

A semiconductor apparatus according to claim 15, wherein said output driving unit comprises: a first MOS transistor, of a first conductivity type, having a source connected to a first operating potential, a gate connected to the input of said output driving unit and a drain connected to the output of said output driving unit; and a second MOS transistor, of a second conductivity type opposite to said first conductivity type, having a source connected to a second operating potential, a gate connected to the input of said output driving unit and a drain connected to the output of said output driving unit.

Claim 30

A semiconductor apparatus according to claim 27, wherein absolute values of gate threshold voltages of said first and second MOS transistors are smaller than those of other MOS transistors included in said CMOS integrated circuit.