US5926436A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1998-02-03
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Granted: 1999-07-20
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Expires: 2018-02-03
Abstract
Abstract A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit, so that the memory access operations for the memory cell group are controlled.
Inventors
- 👤 Haruki Toda
- 👤 Shozo Saito
- 👤 Kaoru Tokushige
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:42
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1072; G11C7/1015; G11C7/1018; G11C7/22
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
285 words
A method for accessing a clock synchronous DRAM (dynamic random access memory), which includes a plurality of memory cell blocks in which dynamic memory cells are arranged in a matrix form, wherein the memory cell blocks in a same group are synchronously activated and the memory cells of the memory cell blocks consecutively output data in response to a basic clock signal, the method comprising the steps of: generating internal basic clock signals, corresponding in number, to groups of the memory cell blocks by frequency-dividing the basic clock signal and shifting phases of resultant signals by an integral multiple of a phase of the basic clock signal such that the resultant signals overlap each other; externally designating a head address of a memory cell block and a head cycle, for accessing the memory cell blocks; selecting the internal basic clock signals and producing circuit control clock signals corresponding in number to the groups of the memory cell blocks, based on the head address, the head cycle, the number of memory cell blocks, and the number of groups of the memory cell blocks, such that the circuit control clock signals are associated with the internal basic clock signals, respectively; selecting the groups of the memory cell blocks in sequence in a predetermined order, on the basis of the circuit control clock signals and signals continuously counted up in accordance with the basic clock signal; activating the groups of the memory cell blocks in sequence every predetermined number of cycles; and starting consecutive output of data from the memory cells of the memory cell block designated with the head address, from the head cycle of the basic clock signal, in response to a read-out/write-in signal supplied externally.
Claim 2
Independent Claim
285 words
A method for accessing a clock synchronous DRAM (dynamic random access memory), which includes a plurality of memory cell blocks in which dynamic memory cells are arranged in a matrix form, wherein the memory cell blocks in a same group are synchronously activated and the memory cells of the memory cell blocks consecutively output data in response to a basic clock signal, the method comprising the steps of: generating internal basic clock signals, corresponding in number, to groups of the memory cell blocks by frequency-dividing the basic clock signal and shifting phases of resultant signals by an integral multiple of a phase of the basic clock signal such that the resultant signals overlap each other; externally designating a head address of a memory cell block and a head cycle, for accessing the memory cell blocks; selecting the internal basic clock signals and producing circuit control clock signals corresponding in number to the groups of the memory cell blocks, based on the head address, the head cycle, the number of memory cell blocks, and the number of groups of the memory cell blocks, such that the circuit control clock signals are associated with the internal basic clock signals, respectively; selecting the groups of the memory cell blocks in sequence in a predetermined order, on the basis of the circuit control clock signals and signals continuously counted up in accordance with the basic clock signal; activating the groups of the memory cell blocks in sequence every predetermined number of cycles; and starting consecutive output of data from the memory cells of the memory cell block designated with the head address, from the head cycle of the basic clock signal, in response to a read-out/write-in signal supplied externally.
Claim 3
Dependent Claim
14 words
The method according to claim 1, wherein the basic clock signal is externally supplied.
Claim 4
Dependent Claim
18 words
The method according to claim 1, wherein the head address is designated using part of an address signal.
Claim 5
Dependent Claim
36 words
The method according to claim 1, wherein the signals continuously counted up in accordance with the basic clock signals are outputs from a serial counter and select column decoders corresponding to the memory cell blocks, respectively.
Claim 6
Dependent Claim
88 words
The method according to claim 1, further comprising the step of maintaining a state of the circuit control signals by generating a plurality of selection signals using signals of lower significance bits of the head address and allowing a control signal to temporarily have a significant level, thereby allowing one of the selection signals to temporarily have a significant level in accordance with a state of the head address, the maintaining step being executed after the step of externally designating the head address and setting the head cycle.
Claim 7
Independent Claim
264 words
A method for accessing a clock synchronous DRAM (dynamic random access memory), which includes a plurality of memory cell blocks in which dynamic memory cells are arranged in a matrix form, wherein the memory cell blocks in a same group are synchronously activated and the memory cells of the memory cell blocks consecutively output data in response to a basic clock signal, the method comprising the steps of: generating internal basic clock signals, corresponding in number, to groups of the memory cells blocks by frequency-dividing the basic clock signal and shifting phases of resultant signals by an integral multiple of a phase of the basic clock signal such that the resultant signals overlap each other; externally designating a head address of a memory cell block for accessing the memory cell blocks and setting a head cycle in accordance with the number of memory cell blocks and the number of groups of the memory cell blocks; selecting the internal basic clock signals and producing circuit control clock signals corresponding in number to the groups of the memory cell blocks; selecting and activating the groups of the memory cell blocks in sequence in a predetermined order, on the basis of the circuit control clock signals and signals continuously counted up in accordance with the basic clock signal, such that memory cell blocks in a selected group are simultaneously activated; and starting consecutive output of data from the memory cells of the memory cell block designated with the head address, from the head cycle of the basic clock signal, in response to a read-out/write-in signal supplied externally.
Claim 8
Independent Claim
264 words
A method for accessing a clock synchronous DRAM (dynamic random access memory), which includes a plurality of memory cell blocks in which dynamic memory cells are arranged in a matrix form, wherein the memory cell blocks in a same group are synchronously activated and the memory cells of the memory cell blocks consecutively output data in response to a basic clock signal, the method comprising the steps of: generating internal basic clock signals, corresponding in number, to groups of the memory cells blocks by frequency-dividing the basic clock signal and shifting phases of resultant signals by an integral multiple of a phase of the basic clock signal such that the resultant signals overlap each other; externally designating a head address of a memory cell block for accessing the memory cell blocks and setting a head cycle in accordance with the number of memory cell blocks and the number of groups of the memory cell blocks; selecting the internal basic clock signals and producing circuit control clock signals corresponding in number to the groups of the memory cell blocks; selecting and activating the groups of the memory cell blocks in sequence in a predetermined order, on the basis of the circuit control clock signals and signals continuously counted up in accordance with the basic clock signal, such that memory cell blocks in a selected group are simultaneously activated; and starting consecutive output of data from the memory cells of the memory cell block designated with the head address, from the head cycle of the basic clock signal, in response to a read-out/write-in signal supplied externally.
Claim 9
Dependent Claim
14 words
The method according to claim 6, wherein the basic clock signal is externally supplied.
Claim 10
Dependent Claim
18 words
The method according to claim 6, wherein the head address is designated using part of an address signal.
Claim 11
Dependent Claim
89 words
The method according to claim 6, further comprising the step of maintaining a state of the circuit control signals by generating a plurality of selection signals by using signals of lower significant bits of the head address and allowing a control signal to temporarily have a significant level, thereby allowing one of the selection signals to temporarily have a significant level in accordance with a state of the head address, the maintaining step being executed after the steps of externally designating the head address and setting the head cycle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-19 | 2003-01-18 | 2003-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-19 | 2007-01-18 | 2007-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-19 | 2011-01-18 | 2011-07-20 | $7700.00 | Window Closed / Lapsed |