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EP0260897A2
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First-in-first-out memory system
Assignee: Advanced Micro Devices Inc
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Filing: 1987-09-11
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Granted: —
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Expires: 2007-09-11
Abstract
Abstract A first-in-first-out (FIFO) memory system organizes a memory with N word storage locations into M pointer-based random access memories (RAMs), each containing N/M storage locations. A sequence of data words is written into a read out of the M RAMs in a cyclical fashion. An M fold increase in write rate is obtained by an input control logic which causes all M RAMs to be in a different stage of the shift-in cycle at the same time. Similarly, an M fold increase in read rate is obtained by an output control logic which causes all M RAMs to be simulateously in a different stage of the shift-out cycle. The output signals of the RAMs being read are multiplexed to generate the original sequence.
Inventors
- 👤 Barry A. Hoberman
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 09:39
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/16
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
97 words
A first-in-first-out (FIFO) memory system comprising a plurality of random access memories (RAMs), characterized by: means electrically coupled to the plurality of RAMs for writing to sequence of data words in a corresponding sequence of write time periods cyclically into the plurality of RAMs so that at least two of the write time periods overlap; and means electrically coupled to the plurality of RAMs for reading a sequence of data words in a corresponding sequence of read time periods cyclically out of the plurality of RAMs so that at least two of the read time periods overlap.
Claim 2
Dependent Claim
97 words
A first-in-first-out (FIFO) memory system comprising a plurality of random access memories (RAMs), characterized by: means electrically coupled to the plurality of RAMs for writing to sequence of data words in a corresponding sequence of write time periods cyclically into the plurality of RAMs so that at least two of the write time periods overlap; and means electrically coupled to the plurality of RAMs for reading a sequence of data words in a corresponding sequence of read time periods cyclically out of the plurality of RAMs so that at least two of the read time periods overlap.
Claim 3
Dependent Claim
30 words
A FIFO memory system as claimed in claim 1 wherein the means for writing causes each of the write time periods to overlap at least one other write time period.
Claim 4
Dependent Claim
46 words
A FIFO memory system as claimed in claim 1 wherein the plurality of RAMs comprises M RAMs, where M is an integer greater than or equal to 2, and wherein the means for writing causes each write time period to overlap (M-1) other write time periods.
Claim 5
Dependent Claim
33 words
A FIFO memory system as claimed in claim 1, 2 or 3 wherein the means for reading causes each of the read time periods to overlap at least one other read time period.
Claim 6
Dependent Claim
50 words
A FIFO memory system as claimed in claim 1, 2 or 3 wherein the plurality of RAMs comprises M RAMs, where M is a positive integer greater than or equal to 2, and wherein the means for reading causes each read time period to overlap (M-1) other read time periods.
Claim 7
Dependent Claim
94 words
A FIFO memory system as claimed in claim 1 wherein the plurality of RAMs comprises M RAMs R(k), k=0, . . ., (M-1), where M is a positive integer greater than or equal to 2, wherein the sequence of data words comprises data words W(k), k=0, . . ., and data word W(k) is written into RAM (k Mod M) during time period Tk for k=0, . . ., and wherein data word W(k) stored in RAM (k Mod M) is read out of RAM (k Mod M) during time period T'k for k=0.
Claim 8
Dependent Claim
16 words
A FIFO memory system as claimed in claim 6 wherein all M time periods T overlap.
Claim 9
Dependent Claim
104 words
A FIFO memory system as claimed in claim 1 wherein the means for writing comprises: a plurality of write latches corresponding to the plurality of RAMs; an input data buffer for receiving the sequence of data words and for providing the sequence of data words to the plurality of write latches; and an input control logic circuit connected to the plurality of latches for causing the sequence of data words to be latched cyclically into the plurality of write latches, each of the plurality of write latches providing a word from the sequence latched therein to the corresponding RAM in the plurality of RAMs.
Claim 10
Dependent Claim
65 words
A FIFO memory system as claimed in claim 8 wherein the input control logic circuit includes a ring counter for generating a plurality of write signals corresponding to the plurality of latches, each of the write signals having the same frequency and each being a linear translate of the other, each of the write signals being provided as the clock signal to its corresponding latch.
Claim 11
Dependent Claim
45 words
A FIFO memory system as claimed in claim 1 wherein the means for writing includes a write ring pointer for directing a data word being written into a given RAM in the plurality of RAMs to a selected empty memory cell in the given RAM.
Claim 12
Dependent Claim
124 words
A FIFO memory system as claimed in claim 1, 2 or 3 wherein the means for reading comprises; a plurality of read latches corresponding to the plurality of RAMs; a multiplexer for receiving the sequence of data words; an output data buffer for receiving the sequence of data words from the multiplexer and for providing the sequence of the data words to external circuitry; and an output control logic circuit coupled to the plurality of read latches and to the multiplexer for causing the sequence of data words to be latched cyclically into each of the plurality of read latches, each of the plurality of read latches providing a word from the sequence latch therein to the corresponding RAM in the plurality of RAMs.
Claim 13
Dependent Claim
72 words
A FIFO memory system as claimed in claim 11 wherein the output control logic includes a ring counter for generating a plurality of read signals corresponding to the plurality of latches, each of the read signals having the same frequency and each being a linear translate of the other, each of the read signals being provided as the clock signal to its corresponding latch and as a control signal to the multiplexer.
References Cited (Backward Citations)
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