US5058074A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit including programmable circuit
Assignee: Kawasaki Microelectronics Inc
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Filing: 1990-02-16
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Granted: 1991-10-15
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Expires: 2010-02-16
Abstract
Abstract In an integrated circuit comprising a programmable circuit and a non-volatile chip formed on the same chip, a volatile memory, instead of the non-volatile memory, is disposed within the programmable circuit, and a circuit is further provided for transferring program data between the non-volatile memory and the volatile memory. By placing the non-volatile memory outside the programmable circuit, the interior of the programmable circuit is not exposed to the high voltage required for writing to the non-volatile memory, and program data can be rapidly and easily transfered between the memories.
Inventors
- 👤 Makoto Sakamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:08
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736; G; G11; G11C; G11C11/00; G11C11/005; G11C14/00; G11C16/00; G11C16/02; G11C16/06; G11C16/10
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
94 words
An integrated circuit comprising: (a) a volatile memory device disposed in a programmable circuit on a chip for storing program data concerning said programmable circuit; (b) a non-volatile memory device disposed externally of said programmable circuit on said chip, said non-volatile memory device permitting said program data to be written therein from a write source external to said chip, and; means for selectively transferring to said volatile memory device either program data written in said non-volatile memory device, or program data supplied from a terminal connectable to a data source external to said chip.
Claim 2
Dependent Claim
94 words
An integrated circuit comprising: (a) a volatile memory device disposed in a programmable circuit on a chip for storing program data concerning said programmable circuit; (b) a non-volatile memory device disposed externally of said programmable circuit on said chip, said non-volatile memory device permitting said program data to be written therein from a write source external to said chip, and; means for selectively transferring to said volatile memory device either program data written in said non-volatile memory device, or program data supplied from a terminal connectable to a data source external to said chip.
Claim 3
Dependent Claim
164 words
An integrated circuit according to claim 1 wherein said means for transferring program data comprises a clock source for producing a first clock signal; a frequency divider circuit for dividing said first clock signal to produce a second clock signal; a counter for counting said second clock signal and generating an address in synchronism with said second clock signal; a first decoder for decoding said address as a read address to select a word line of said non-volatile memory device; a second decoder for decoding said address as a write address to select a word line of said volatile memory device; a sensing circuit for reading the data stored in said non-volatile memory device in synchronism with said second clock signal; an input switching/writing circuit for selecting either the program data read by said sensing circuit or program data from the external data source responsive to a control signal generated externally of said chip for driving a bit line of said volatile memory device.
Claim 4
Dependent Claim
33 words
An integrated circuit according to claim 1 wherein said means for transferring program data includes a circuit for transferring the program data stored in said volatile memory device to said non-volatile memory device.
Claim 5
Dependent Claim
103 words
An integrated circuit according to claim 3 wherein said circuit for transferring the program data stored in said volatile memory device to said non-volatile memory device comprises a second sensing circuit for reading the data stored in said volatile memory device in synchronism with said second clock signal, a second input switching/writing circuit responsive to a control signal generated externally of said chip for selecting either program data read by said second sensing circuit or program data from the external data source, and a voltage multiplier connected to said second input switching/writing circuit for generating high write voltages for said non-volatile memory device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-14 | 1995-04-15 | 1995-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-14 | 1999-04-15 | 1999-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-14 | 2003-04-15 | 2003-10-15 | $7700.00 | Window Closed / Lapsed |