Eprom controlled tri-port transceiver

Claim 2

An erasable programmable logic device (EPLD) for receiving, switching and transmitting data among a plurality of channels, comprising: a programmable logic array (PLA) including a memory and a macro-architecture circuit for providing control signals; a transceiver circuit coupled to said PLA for receiving said control signals and also coupled to said plurality of channels, said transceiver circuit comprising for each channel: (a) a latch to receive and store an input to said channel; (b) a first multiplexer coupled to receive latched outputs from said latches of other said channels, such that one of said other latched outputs is selected; (c) a driver coupled to receive said selected output from said first multiplexer and coupled to transmit said selected output onto said channel; wherein for each said channel, its input is latched and coupled to various said first multiplexers of other said channels for switching its input onto other said channels; whereby data on each of said channels is switched for transmission onto other said channels.

Claim 3

The EPLD of claim 1, wherein said control signals from said PLA provide for latching each of said channel inputs through its latch; provide selecting of latched outputs from said first multiplexer; and activates said drivers for transmission.

Claim 4

The EPLD of claim 1, further including for each channel, a second multiplexer coupled between said first multiplexer and said driver for selecting either a non-inverted or an inverted output of said first multiplexer.

Claim 5

The EPLD of claim 3, further including a feedback multiplexer, wherein said latched outputs of each channel are coupled as inputs to said feedback multiplexer, such that said feedback multiplexer selects one of said latched outputs as a feedback signal to said PLA to determine next state generation of said control signals.

Claim 6

The EPLD of claim 4, wherein said control signals from said PLA provide control of said latches, multiplexers and activation of said drivers.

Claim 7

The EPLD of claim 5, further including a plurality of said transceiver circuits for simultaneous transfer of information when each said channel is comprised of a plurality of data lines.

Claim 8

The EPLD of claim 6, wherein said PLA is implemented using EPROM technology.

Claim 9

The EPLD of claim 7, being implemented on a single semiconductor chip.

Claim 10

The EPLD of claim 1, wherein at least one of said drivers has a programmable output impedance.

Claim 11

A multiple-port transceiver for receiving, switching and transmitting digital data among said ports, said transceiver being controlled by control signals from a programmable logic array (PLA) implemented using EPROM technology, comprising: for each said port: (a) input means to receive an input to said port; (b) first multiplexer means coupled to receive output from said input means of other said ports, such that one of said output from other said input means is selected; (c) driver means coupled to receive said selected output from said first multiplexer means and coupled to transmit said selected output onto said port; wherein for each said port, its input is propagated to various said first multiplexer means of other said ports for switching its input onto other said ports; whereby digital data on each of said ports is switched for transmission onto other said ports.

Claim 12

A multiple-port transceiver for receiving, switching and transmitting digital data among said ports, said transceiver being controlled by control signals from a programmable logic array (PLA) implemented using EPROM technology, comprising: for each said port: (a) input means to receive an input to said port; (b) first multiplexer means coupled to receive output from said input means of other said ports, such that one of said output from other said input means is selected; (c) driver means coupled to receive said selected output from said first multiplexer means and coupled to transmit said selected output onto said port; wherein for each said port, its input is propagated to various said first multiplexer means of other said ports for switching its input onto other said ports; whereby digital data on each of said ports is switched for transmission onto other said ports.

Claim 13

The transceiver of claim 10, further including for each channel, second multiplexer means coupled between said first multiplexer means and said driver means for selecting either a non-inverted or an inverted output of said first multiplexer means.

Claim 14

The transceiver of claim 11, further including feedback multiplexer means, wherein said inputs of each said port are coupled to said feedback multiplexer means such that said feedback multiplexer means select one of said inputs as a feedback signal to said PLA to determine next state generation of said control signals.

Claim 15

The transceiver of claim 12, wherein said control signals from said PLA provide control of said input means, multiplexer means and activation of said driver means.

Claim 16

A three-port transceiver for receiving, switching and transmitting digital data among said ports, said transceiver being controlled by control signals from a programmable logic array (PLA) implemented using EPROM technology, comprising: a first latch coupled to a first port for latching a first input signal present on said first port; a second latch coupled to a second port for coupling a second input signal present on said second port; a third latch coupled to a third port for latching a third input signal present on said third port; a first multiplexer coupled to said second and third latches for receiving said second and third input signals and selecting one of said second and third input signals as an output of said first multiplexer; a first driver coupled to said first multiplexer for driving said first multiplexer output onto said first port, such that one of said second or third input signals is switched onto said first port; a second multiplexer coupled to said first and third latches for receiving said first and third input signals and selecting one of said first and third input signals as an output of said second multiplexer; a second driver coupled to said second multiplexer for driving said second multiplexer output onto said second port, such that one of said second or third input signals is switched onto said second port; a third multiplexer coupled to said first and second latches for receiving said first and second input signals and selecting one of said first and second input signals as an output of said third multiplexer; a third driver coupled to said third multiplexer for driving said third multiplexer output onto said third port, such that one of said first or second input signals is switched onto said first port; wherein for each said port, its input is latched to said multiplexers of other said ports for switching its input onto other said ports; whereby digital data on each of said ports is switched for transmission onto other said ports.

Claim 17

A three-port transceiver for receiving, switching and transmitting digital data among said ports, said transceiver being controlled by control signals from a programmable logic array (PLA) implemented using EPROM technology, comprising: a first latch coupled to a first port for latching a first input signal present on said first port; a second latch coupled to a second port for coupling a second input signal present on said second port; a third latch coupled to a third port for latching a third input signal present on said third port; a first multiplexer coupled to said second and third latches for receiving said second and third input signals and selecting one of said second and third input signals as an output of said first multiplexer; a first driver coupled to said first multiplexer for driving said first multiplexer output onto said first port, such that one of said second or third input signals is switched onto said first port; a second multiplexer coupled to said first and third latches for receiving said first and third input signals and selecting one of said first and third input signals as an output of said second multiplexer; a second driver coupled to said second multiplexer for driving said second multiplexer output onto said second port, such that one of said second or third input signals is switched onto said second port; a third multiplexer coupled to said first and second latches for receiving said first and second input signals and selecting one of said first and second input signals as an output of said third multiplexer; a third driver coupled to said third multiplexer for driving said third multiplexer output onto said third port, such that one of said first or second input signals is switched onto said first port; wherein for each said port, its input is latched to said multiplexers of other said ports for switching its input onto other said ports; whereby digital data on each of said ports is switched for transmission onto other said ports.

Claim 18

The tri-port transceiver of claim 14, further including: a fourth multiplexer coupled between said first multiplexer and said first driver for selecting either a non-inverted or an inverted output of said first multiplexer; a fifth multiplexer coupled between said second multiplexer and said second driver for selecting either a non-inverted or an inverted output of said second multiplexer; a sixth multiplexer coupled between said third multiplexer and said third driver for selecting either a non-inverted or an inverted output of said third multiplexer.

Claim 19

The tri-port transceiver of claim 15, further including a seventh multiplexer coupled to said first, second and third latches for selecting one of said input signals as an output of said seventh multiplexer, such that said seventh multiplexer provides a feedback signal to said PLA to determine next state generation of said control signals.

Claim 20

The tri-port transceiver of claim 16, wherein said first, second and third drivers are three-state drivers having a high impedance third-state when each of said drivers is made inactive.

Claim 21

The tri-port transceiver of claim 17, wherein said control signals from said PLA provide control of said latches, multiplexers and activation of said drivers.

Claim 22

The tri-port transceiver of claim 18, further including a first, second and third buffers, each said buffer being coupled between each of said port and its respective latch for buffering said respective input.

Claim 23

The tri-port transceiver of claim 19, further including an eighth and ninth multiplexer; said eighth multiplexer coupled to select either a latched or an unlatched first input signal as an input to said second multiplexer; said ninth multiplexer coupled to select either a latched or an unlatched second input signal as an input to said first multiplexer;

Claim 24

The tri-port transceiver of claim 19, being implemented on a single semiconductor chip.

Claim 25

The tri-port transceiver of claim 16, wherein any of said first, second and third drivers is a three-state driver having a programmable output impedance.