Programmable logic device

Claim 2

A logic device having a plurality of external terminals and a plurality of input/output ports, comprising: programmable array means responsive to signals applied to said external terminals of said device for generating a plurality of logic signals; a plurality of programmable output cell means, each receiving programmably selectable ones of said logic signals, for storing predetermined ones of said logic signals, and for generating a signal therefrom at a predetermined one of said input/output ports; a plurality of storage cell means, each receiving programmably selectable ones of said logic signals, for storing predetermined ones of said logic signals and for generating a signal therefrom; counter means, receiving programmably selectable ones of said logic signals, for storing a count value therefrom, for selectably incrementing or decrementing said count value, and for generating therefrom counting signals indicative of said count value; and means receiving said counting signals and programmably-selectable ones of said logic signals, for selectably storing said count value in a last-in, first-out stack, for removing the last-in contents of said stack, and for generating therefrom signals indicative of said last-in contents; said counter means also receiving said signals generated by said stack means.

Claim 3

A logic device according to claim 1 wherein said programmable array means is further responsive to said signals generated by predetermined ones of said programmable output cell means, said storage cell means and said counter means.

Claim 4

A logic device according to claim 1 wherein said plurality of logic signals generated by said programmable array means includes a plurality of load address signals, a load control signal, and a push and a pop signal, and wherein said counter means is further responsive to said load address and load control signals, and wherein said counter means and said stack means are further responsive to said push and pop signals, whereupon reception of said load control signal causes said counter means to replace the contents of said counter means with said load address; and whereupon reception of said push, respectively, said pop signal, causes said counter means to generate said signals indicative of said count value, conduct said signals to said stack means for storage therein, respectively, said stack means to remove said count value, generate signals therefrom, and conduct said signals to said counter for storage therein.

Claim 5

A logic device according to claim 1 wherein said plurality of logic signals generated by said programmable array means includes a clear signal and wherein said counter means is further responsive to said clear signal, and whereupon reception of said clear signal causes said counter means to replace the contents of said counter means with a predetermined count value.

Claim 6

A logic device according to claim 4 wherein said stack means is further responsive to said clear signal, and whereupon reception of said clear signal causes all contents of said stack means to be removed.

Claim 7

A logic device having a plurality of external terminals and a plurality of input/output ports, comprising: programmable array means responsive to signals applied to said external terminals of said device for generating a plurality of logic signals; a plurality of programmable output cell means, each receiving programmably selectable ones of said logic signals, for storing predetermined ones of said logic signals, and for generating a signal therefrom at a predetermined one of said input/output ports; a plurality of storage cell means, each receiving programmably selectable ones of said logic signals, for storing predetermined ones of said logic signals and for generating a signal therefrom; and memory means receiving predetermined ones of said logic signals, "data" signals, for selectably storing said data signals and for generating signals indicative of said stored data.

Claim 8

A logic device having a plurality of external terminals and a plurality of input/output ports, comprising: programmable array means responsive to signals applied to said external terminals of said device for generating a plurality of logic signals; a plurality of programmable output cell means, each receiving programmably selectable ones of said logic signals, for storing predetermined ones of said logic signals, and for generating a signal therefrom at a predetermined one of said input/output ports; a plurality of storage cell means, each receiving programmably selectable ones of said logic signals, for storing predetermined ones of said logic signals and for generating a signal therefrom; and memory means receiving predetermined ones of said logic signals, "data" signals, for selectably storing said data signals and for generating signals indicative of said stored data.

Claim 9

A logic device according to claim 6 wherein said programmable array means is further responsive to said signals generated by predetermined ones of said programmable output cell means, said storage cell means and said memory means.

Claim 10

A logic device according to claim 6 wherein said plurality of logic signals generated by said programmable array means includes a plurality of memory address and write enable signals and wherein said memory means has a plurality of storage locations each having a predetermined address, said memory means further responsive to said memory address and write enable signals, and whereupon reception of said write enable signal causes said memory means to replace the contents of said storage location having the address represented by said address signals with said data.

Claim 11

A logic device according to claim 6 wherein said memory means is a random access memory.

Claim 12

A logic device according to claim 6 further including: counter means, receiving programmably selectable ones of said logic signals, for storing a count value therefrom, for selectably incrementing or decrementing said count value, and for generating therefrom counting signals indicative of said count value.

Claim 13

A logic device according to claim 10 wherein said programmable array means is further reponsive to said signals generated by said counter means.

Claim 14

A logic device according to claim 10 wherein said plurality of logic signals generated by said programmable array means includes a clear signal and wherein said counter means is further responsive to said clear signal, and whereupon reception of said clear signal causes said counter means to replace the contents of said counter means with a predetermined count value.

Claim 15

A logic device according to claim 10 further including: means receiving said counting signals and programmably-selectable ones of said logic signals, for selectably storing said count value in a last-in, first-out stack, for removing the last-in contents of said stack, and for generating therefrom signals indicative of said last-in contents; said counter means also receiving said signals generated by said stack means.

Claim 16

A logic device according to claim 13 wherein said plurality of logic signals generated by said programmable array means includes a plurality of load address signals, a load control signal, and a push and a pop signal, and wherein said counter means is further responsive to said load address and load control signals, and wherein said counter means and said stack means are further responsive to said push and pop signals, whereupon reception of said load control signal causes said counter means to replace the contents of said counter means with said load address; and whereupon reception of said push, respectively, said pop signal, causes said counter means to generate said signals indicative of said count value, conduct said signals to said stack means for storage therein, respectively, said stack means to remove said count value, generate signals therefrom, and conduct said signals to said counter for storage therein.

Claim 17

A logic device according to claim 13 wherein said plurality of logic signals generated by said programmable array means includes a clear signal and wherein said counter means is further responsive to said clear signal, and whereupon reception of said clear signal causes said counter means to replace the contents of said counter means with a predetermined count value.

Claim 18

A logic device according to claim 15 wherein said stack means is further responsive to said clear signal, and whereupon reception of said clear signal causes all contents of said stack means to be removed.

Claim 19

A programmable logic device having a plurality of input/output ports, comprising: a plurality of programmable logic cell means dynamically generating logic signals, and a second plurality of first and second programmable combinatorial logic means for combining a subset of logic signals and for generating a plurality of combinatorial signals therefrom; a plurality of programmable output cell means, each receiving programmably selectable ones of said combinatorial signals generated by said first programmable combinatorial logic means, for storing predetermined ones of said combinatorial signals, and for generating a signal therefrom at a predetermined one of said input/output ports; a plurality of storage cell means, each receiving programmably selectable ones of said combinatorial signals generated by said second programmable combinatorial logic means, for storing predetermined ones of said combinatorial signals, and for generating a signal therefrom; counter means, receiving programmably selectable ones of said combinatorial signals generated by said second programmable combinatorial logic means, for storing a count value therefrom, for selectably incrementing or decrementing said count value, and for generating therefrom counting signals indicative of said count value; and means receiving said counting signals and programmably selectable ones of said combinatorial signals generated by said second programmable combinatorial logic means, for selectably storing said count value in a last-in, first-out stack, for removing the last-in contents of said stack, and for generating therefrom signals indicative of said last-in contents; said counter means also receiving said signals generated by said stack means.

Claim 20

A programmable logic device having a plurality of input/output ports, comprising: a plurality of programmable logic cell means dynamically generating logic signals, and a second plurality of first and second programmable combinatorial logic means for combining a subset of logic signals and for generating a plurality of combinatorial signals therefrom; a plurality of programmable output cell means, each receiving programmably selectable ones of said combinatorial signals generated by said first programmable combinatorial logic means, for storing predetermined ones of said combinatorial signals, and for generating a signal therefrom at a predetermined one of said input/output ports; a plurality of storage cell means, each receiving programmably selectable ones of said combinatorial signals generated by said second programmable combinatorial logic means, for storing predetermined ones of said combinatorial signals, and for generating a signal therefrom; counter means, receiving programmably selectable ones of said combinatorial signals generated by said second programmable combinatorial logic means, for storing a count value therefrom, for selectably incrementing or decrementing said count value, and for generating therefrom counting signals indicative of said count value; and means receiving said counting signals and programmably selectable ones of said combinatorial signals generated by said second programmable combinatorial logic means, for selectably storing said count value in a last-in, first-out stack, for removing the last-in contents of said stack, and for generating therefrom signals indicative of said last-in contents; said counter means also receiving said signals generated by said stack means.

Claim 21

A programmable logic device according to claim 17 wherein said plurality of logic cell means is further responsive to said signals generated by predetermined ones of said programmable output cell means, said storage cell means and said counter means.

Claim 22

A programmable logic device according to claim 17 wherein said combinatorial signals generated by said second programmable combinatorial logic means includes a plurality of load address signals, a load control signal, and a push and a pop signal, and wherein said counter means is further responsive to said load address and load control signals, and wherein said counter means and said stack means are further responsive to said push and pop signals, whereupon reception of said load control signal causes said counter means to replace the contents of said counter means with said load address; and whereupon reception of said push, respectively, said pop signal, causes said counter means to generate said signals indicative of said count value, conduct said signals to said stack means for storage therein, respectively, said stack means to remove said count value, generate signals therefrom, and conduct said signals to said counter for storage therein.

Claim 23

A programmable logic device according to claim 17 wherein said combinatorial signals generated by said second programmable combinatorial means includes a clear signal and wherein said counter means is further responsive to said clear signal, and whereupon reception of said clear signal causes said counter means to replace the contents of said counter means with a predetermined count value.

Claim 24

A programmable logic device according to claim 17 wherein said programmable logic cell means is a programmable AND array.

Claim 25

A programmable logic device according to claim 17 wherein said first and second programmable combinatorial logic means are programmable OR arrays.

Claim 26

A programmable logic device according to claim 17 wherein said stack means is further responsive to said clear signal, and whereupon reception of said clear signal causes all contents of said stack means to be removed.

Claim 27

A programmable logic device according to claim 17 wherein said programmable output cell means comprises: register means, responsive to a clock signal, receiving said combinatorial logic signal, for registering said logic signal and for generating therefrom a registered signal; output enable control means responsive to a predetermined one of said logic signals generated by said logic cell means and the status of a programmable fusible link, for selectively generating therefrom an output enable signal and an output disable signal, in response to said predetermined logic signal; and input/output means receiving said output signal, responsive to said output enable and disable signals, for selectively generating therefrom said output signal at said predetermined input/output port, and for receiving a signal received at said predetermined input/output port.

Claim 28

A programmable logic device having a plurality of input/output ports, comprising: a plurality of programmable logic cell means dynamically generating logic signals, and a second plurality of first and second programmable combinatorial logic means for combining a subset of logic signals and for generating a plurality of combinatorial signals therefrom; a plurality of programmable output cell means, each receiving programmably selectable ones of said combinatorial signals generated by said first programmable combinatorial logic means, for storing predetermined ones of said combinatorial signals, and for generating a signal therefrom at a predetermined one of said input/output ports; a plurality of storage cell means, each receiving programmably selectable ones of said combinatorial signals generated by said second programmable combinatorial logic means, for storing predetermined ones of said combinatorial signals, and for generating a signal therefrom; and memory means receiving predetermined ones of said combinatorial signals generated by said first programmable combinatorial logic means, "data" signals, for selectably storing said data signals and for generating signals indicative of said stored data.

Claim 29

A programmable logic device having a plurality of input/output ports, comprising: a plurality of programmable logic cell means dynamically generating logic signals, and a second plurality of first and second programmable combinatorial logic means for combining a subset of logic signals and for generating a plurality of combinatorial signals therefrom; a plurality of programmable output cell means, each receiving programmably selectable ones of said combinatorial signals generated by said first programmable combinatorial logic means, for storing predetermined ones of said combinatorial signals, and for generating a signal therefrom at a predetermined one of said input/output ports; a plurality of storage cell means, each receiving programmably selectable ones of said combinatorial signals generated by said second programmable combinatorial logic means, for storing predetermined ones of said combinatorial signals, and for generating a signal therefrom; and memory means receiving predetermined ones of said combinatorial signals generated by said first programmable combinatorial logic means, "data" signals, for selectably storing said data signals and for generating signals indicative of said stored data.

Claim 30

A programmable logic device according to claim 25 wherein said plurality of logic cell means is further responsive to said signals generated by predetermined ones of said programmable output cell means, said storage cell means and said memory means.

Claim 31

A programmable logic device according to claim 25 wherein said combinatorial signals generated by said first programmable combinatorial logic means includes a a plurality of memory address and write enable signals and wherein said memory means has a plurality of storage locations each having a predetermined address, said memory means further responsive to said memory address and write enable signals, and whereupon reception of said write enable signal causes said memory means to replace the contents of said storage location having the address represented by said address signals with said data.

Claim 32

A programmable logic device according to claim 25 wherein said programmable logic cell means is a programmable AND array.

Claim 33

A programmable logic device according to claim 25 wherein said first and second programmable combinatorial logic means are programmable OR arrays.

Claim 34

A programmable logic device according to claim 25 wherein said memory means is a random access memory.

Claim 35

A programmable logic device according to claim 25 wherein said programmable output cell means comprises: register means, responsive to a clock signal, receiving said combinatorial logic signal, for registering said logic signal and for generating therefrom a registered signal; output enable control means responsive to a predetermined one of said logic signals generated by said logic cell means and the status of a programmable fusible link, for selectively generating therefrom an output enable signal and an output disable signal, in response to said predetermined logic signal; and input/output means receiving said output signal, responsive to said output enable and disable signals, for selectively generating therefrom said output signal at said predetermined input/output port, and for receiving a signal received at said predetermined input/output port.

Claim 36

A logic device according to claim 25 further including: counter means receiving programmably selectable ones of said combinatorial signals, generated by said second programmable combinatorial logic means, for storing a count value therefrom, for selectably incrementing or decrementing said count value, and for generating therefrom counting signals indicative of said count value.

Claim 37

A logic device according to claim 32 wherein said plurality of logic cell means is further responsive to said signals generated by said counter means.

Claim 38

A logic device according to claim 32 wherein said combinatorial signals generated by said second combinatorial logic means includes a clear signal and wherein said counter means is further responsive to said clear signal, and whereupon reception of said clear signal causes said counter means to replace the contents of said counter means with a predetermined counter value.

Claim 39

A logic device according to claim 32 further including: means receiving said counting signals and programmably selectable ones of said combinatorial logic signals generated by said second programmable combinatorial logic means, for selectably storing said count value in a last-in, first-out stack, for removing the last-in contents of said stack, and for generating therefrom signals indicative of said last-in contents; said counter means also receiving said signals generated by said stack means.

Claim 40

A logic device according to claim 35 wherein said combinatorial signals generated by said second combinatorial logic means inclues a plurality of load address signals, a load control signal, and a push and a pop signal, and wherein said counter means is further responsive to said load address and load control signals, and wherein said counter means and said stack means are further responsive to said push and pop signals, whereupon reception of said load control signal causes said counter means to replace the contents of said counter means with said load address; and whereupon reception of said push, respectively, said pop signal, causes said counter means to generate said signals indicative of said count value, conduct said signals to said stack means for storage therein, respectively, said stack means to remove said count value, generate signals therefrom, and conduct said signals to said counter for storage therein.

Claim 41

A logic device according to claim 35 wherein said combinatorial signals generated by said second combinatorial logic means further includes a clear signal and wherein said counter means is further responsive to said clear signal, and whereupon reception of said clear signal causes said counter means to replace the contents of said counter means with a predetermined count value.

Claim 42

A logic device according to claim 37 wherein said stack means if further responsive to said clear signal, and whereupon reception of said clear signal causes all contents of said stack means to be removed.

Claim 43

A logic device having a plurality of external terminals and a plurality of input/output ports, comprising: programmable array means responsive to signals applied to said external terminals of said device for generating a plurality of logic signals; a plurality of programmable output cell means, each receiving programmably selectable ones of said logic signals, for storing predetermined ones of said logic signals, and for generating a signal therefrom at a predetermined one of said input/output ports; a plurality of storage cell means, each receiving programmably selectable ones of said logic signals, for storing predetermined ones of said logic signals and for generating a signal therefrom; counter means, receiving programmably selectable ones of said logic signals, for storing a count value therefrom, for selectably incrementing or decrementing said count value, and for generating therefrom counting signals indicative of said count value; means receiving said counting signals and programmably-selectable ones of said logic signals, for selectably storing said count value in a last-in, first-out stack, for removing the last-in contents of said stack, and for generating therefrom signals indicative of said last-in contents; said counter means also receiving said signals generated by said stack means; and memory means receiving predetermined ones of said logic signals, "data" signals, for selectably storing said data signals and for generating signals indicative of said stored data.

Claim 44

A logic device having a plurality of external terminals and a plurality of input/output ports, comprising: programmable array means responsive to signals applied to said external terminals of said device for generating a plurality of logic signals; a plurality of programmable output cell means, each receiving programmably selectable ones of said logic signals, for storing predetermined ones of said logic signals, and for generating a signal therefrom at a predetermined one of said input/output ports; a plurality of storage cell means, each receiving programmably selectable ones of said logic signals, for storing predetermined ones of said logic signals and for generating a signal therefrom; counter means, receiving programmably selectable ones of said logic signals, for storing a count value therefrom, for selectably incrementing or decrementing said count value, and for generating therefrom counting signals indicative of said count value; means receiving said counting signals and programmably-selectable ones of said logic signals, for selectably storing said count value in a last-in, first-out stack, for removing the last-in contents of said stack, and for generating therefrom signals indicative of said last-in contents; said counter means also receiving said signals generated by said stack means; and memory means receiving predetermined ones of said logic signals, "data" signals, for selectably storing said data signals and for generating signals indicative of said stored data.

Claim 45

A logic device according to claim 39 wherein said programmable array means is further responsive to said signals generated by predetermined ones of said programmable output cell means, said storage cell means and said memory means.

Claim 46

A logic device according to claim 39 wherein said plurality of logic signals generated by said programmable array means includes a plurality of load address signals, a load control signal, and a push and a pop signal, and wherein said counter means is further responsive to said load address and load control signals, and wherein said counter means and said stack means are further responsive to said push and pop signals, whereupon reception of said load control signal causes said counter means to replace the contents of said counter means with said load address; and whereupon reception of said push, respectively, said pop signal, causes said counter means to generate said signals indicative of said count value, conduct said signals to said stack means for storage therein, respectively, said stack means to remove said count value, generate signals therefrom, and conduct said signals to said counter for storage therein.

Claim 47

A logic device according to claim 39 wherein said plurality of logic signals generated by said programmable array means includes a plurality of memory address and write enable signals and wherein said memory means has a plurality of storage locations each having a predetermined address, said memory means further responsive to said memory address and write enable signals, and whereupon reception of said write enable signal causes said memory means to replace the contents of said storage location having the address represented by said address signals with said data.

Claim 48

A logic device according to claim 39 herein said plurality of logic signals generated by said programmable array means includes a clear signal and wherein said counter means is further responisive to said clear signal, and whereupon reception of said clear signal causes said counter means to replace the contents of said counter means with a predetermined count value.

Claim 51

An n-state machine design method according to claim 44 further including the subroutine-return steps: d) loading said counter with the contents of the top of said stack (pop); and e) decrementing (modulo p) said stack pointer.

Claim 52

An n-state machine design method according to claim 44 further including the clear step: f) clearing said stack with a predetermined value by applying signals to said AND array.

Claim 55

A memory-write method according to claim 47 further including the memory-read steps: j) generating a plurality of read address signals by applying signals to said AND array; k) reading the contents of said memory at said address generated at step (j).