EP0307912A2
Expired / Lapsed
EP
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Programmable logic device
Assignee: Fujitsu VLSI Ltd
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Filing: 1988-09-16
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Granted: —
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Expires: 2008-09-16
Abstract
Abstract A programmable logic device includes an input/output buffer (23), a logic array (26, 29), switches (24) for switching signal lines provided between the logic array and the input/output buffer and feedback lines between an input and output of the logic array so as to alter the logic operation. Switching operations of the switches such as an open/close operation and a selection operation, are determined by contents stored in a plurality of non-volatile memory elements (31) arranged like a matrix which are provided for the respective switches. The contents of the memory elements are read out and stored in registers. The contents of the non-volatile memory elements stored in the registers are applied to control terminals of the switches.
Inventors
- 👤 Kiyoshi Itano
- 👤 Kohji Shimbayashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 02:04
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
198 words
A programmable logic device comprising input/output buffer means (23) for passing an input signal and output signal with respect to an external circuit; logic array means (26, 29) for performing a logic operation for a signal applied thereto; and switching means (24) including switches (141 - 157) for switching signal lines provided between the logic array means and the input/output buffer means and feedback lines between an input and an output of the logic array means so as to alter the logic operation, characterized in that the device comprises matrix means (56) comprising a plurality of non-volatile memory elements (62) arranged like a matrix being provided for the respective switches, a memory content stored in each of the non-volatile memory elements being used for controlling an switching operation of the corresponding switch; read-out means (40, 42, 48, 52, 57, 58) for reading out the contents of the non-volatile memory elements; and register means (81 - 83) for storing the contents of the non-volatile memory elements (62) read out by the read-out means, and in that switching operations of the switches (141 - 157) are controlled by the contents of the non-volatile memory elements stored in the register means.
Claim 2
Dependent Claim
198 words
A programmable logic device comprising input/output buffer means (23) for passing an input signal and output signal with respect to an external circuit; logic array means (26, 29) for performing a logic operation for a signal applied thereto; and switching means (24) including switches (141 - 157) for switching signal lines provided between the logic array means and the input/output buffer means and feedback lines between an input and an output of the logic array means so as to alter the logic operation, characterized in that the device comprises matrix means (56) comprising a plurality of non-volatile memory elements (62) arranged like a matrix being provided for the respective switches, a memory content stored in each of the non-volatile memory elements being used for controlling an switching operation of the corresponding switch; read-out means (40, 42, 48, 52, 57, 58) for reading out the contents of the non-volatile memory elements; and register means (81 - 83) for storing the contents of the non-volatile memory elements (62) read out by the read-out means, and in that switching operations of the switches (141 - 157) are controlled by the contents of the non-volatile memory elements stored in the register means.
Claim 3
Dependent Claim
51 words
A programmable logic device as claimed in claim 1, characterized in that the read-out means comprises means (40) for detecting power-ON of the device, and when the means (40) detects the power-ON, the read-out means sends the contents of the non-volatile memory elements (62) to the register means (81 - 83).
Claim 4
Dependent Claim
70 words
A programmable logic device as claimed in any of claims 1 to 3, characterized in that the read-out means comprises clock generating means (42) for generating a clock signal, address generating means (48, 53, 54) for generating an address to be supplied to the plurality of non-volatile memory elements, and sense amplify means (58) for amplifying and supplying the read-out contents of the non-volatile memory elements to the register means.
Claim 5
Dependent Claim
35 words
A programmable logic device as claimed in any of claims 1 to 3, characterized in that the device further comprises write-in means (51a, 51b, 67) for writing data into the plurality of non-volatile memory elements.
Claim 6
Dependent Claim
100 words
A programmable logic device as claimed in any of claims 1 to 4, characterized in that the device further comprises verify means (41, 75) for verifying whether the contents of the non-volatile memory elements which are read out from the register means (81 - 83) coincide with the contents of the non-volatile memory elements (62) which are read out therefrom and for controlling the read-out means, based on a verified result, so as to read out the contents of the non-volatile memory elements, starting from a predetermined beginning non-volatile memory element out of the plurality of the non-volatile memory elements.
Claim 7
Dependent Claim
37 words
A programmable logic device as claimed in any of claims 1 to 5, characterized in that the register means (81- 83) comprises a plurality of registers (81 - 83) for storing contents of corresponding non-volatile memory elements.
Claim 8
Dependent Claim
48 words
A programmable logic device as claimed in claim 6, characterized in that the device further comprises means (76) for generating a write enable signal which enables one of the registers in response to a part of an address supplied to the non-volatile memory means from the read-out means.
Claim 9
Dependent Claim
68 words
A programmable logic device as claimed in claim 3, characterized in that the clock generating means generates a first clock signal (ICK1) and a second clock signal (ICK2) which lags behind the first clock signal by 90°, and in that the address generating means (48) supplies the non-volatile memory elements arranged like the matrix with the address in synchronism with the first and clock signals (ICK1 and ICK2).
Claim 10
Dependent Claim
28 words
A programmable logic device as claimed in any of claims 1 to 8, characterized in that the non-volatile memory elements (62) comprises electric programmable random access memory cells.
Claim 11
Dependent Claim
63 words
A programmable logic device as claimed in claim 3, characterized in that the matrix means comprises word lines (60₁ - 60₂₀) and bit lines (61₁ - 61₂₁) between which the non-volatile memory elements are connected, and in that the word lines are coupled with the address generating means (48, 53, 54) and the bit lines are coupled with the sense amplifying means (58).
Claim 12
Dependent Claim
40 words
A programmable logic device as claimed in claim 3, characterized in that the read-out means further comprises multiplexer means (57) for multiplexing the contents of the non-volatile memory elements, and a multiplexed contents are supplied to the sense amplifying means.
References Cited (Backward Citations)
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