Programming circuit for programmable logic array I/O cell

Claim 2

A programmable logic array circuit comprising: an array of programmable memory elements; at least one output cell coupled to at least a portion of said array for providing an output from said array to an output terminal, said output cell having at least one programmable circuit with a programming input; means for generating an architecture programming signal; and means, coupled between said means for generating and at least a first one of said memory elements and responsive to said architecture programming signal, for providing an output of said array to said programming input of said programmable circuit.

Claim 3

The circuit of claim 1 wherein said array has a logic portion containing a plurality of said memory elements and coupled to said output cell for normall operation of said circuit and an architecture portion containing at least said first memory element and coupled to said output cell for programming said programmable circuit and further comprising: means, responsive to said architecture programming signal, for enabling said architecture portion of said array and disabling said logic portion of said array.

Claim 4

The array of claim 1 wherein said means for generating an architecture programming signal is responsive to a power supply level for said array reaching a predetermined threshold value, said architecture programming signal being a pulse provided when said power supply level reaches said value.

Claim 5

The array of claim 3 wherein said means for providing an output of said array to said programming input includes a transistor having its gate coupled to receive said architecture programming signal.

Claim 6

The array of claim 1 further comprising a plurality of said output cells, each of said output cells being coupled to a portion of said array for providing an output from said array to an output terminal, with each said output cell having a plurality of programmable circuits.

Claim 7

The array of claim 1 wherein said programmable circuit comprises a multiplexer and said programming input comprises a select input of said multiplexer.

Claim 8

The array of claim 1 further comprising a plurality of said array outputs coupled to each said output cell, and logic means coupled between said array outputs and said programmable circuit for decoding said array outputs for said programming inputs.

Claim 9

A programmable logic array circuit comprising: an array of programmable memory elements with a logic portion containing a plurality of said memory elements for normal operation of said circuit and an architecture portion; a plurality of output cells, each output cell being coupled to a plurality of output lines from said array for providing an output from said array to an output terminal and including a plurality of programmable circuits, each said programmable circuit having a programming input; power-on sense means for detecting when a power supply level for said programmable logic array circuit passes a predetermined threshold value and generating a pulse signal; means, responsive to said pulse signal, for enabling said architecture portion of said array and disabling said logic portion of said array; a plurality of logic means, coupled between said output lines and said programmable circuits, for decoding signals from said architecture portion on said output lines and providing signals to said programming inputs; and means, coupled between said power-on sense means and said logic means, for enabling said logic means responsive to said pulse signal.

Claim 10

A programmable logic array circuit comprising: an array of programmable memory elements with a logic portion containing a plurality of said memory elements for normal operation of said circuit and an architecture portion; a plurality of output cells, each output cell being coupled to a plurality of output lines from said array for providing an output from said array to an output terminal and including a plurality of programmable circuits, each said programmable circuit having a programming input; power-on sense means for detecting when a power supply level for said programmable logic array circuit passes a predetermined threshold value and generating a pulse signal; means, responsive to said pulse signal, for enabling said architecture portion of said array and disabling said logic portion of said array; a plurality of logic means, coupled between said output lines and said programmable circuits, for decoding signals from said architecture portion on said output lines and providing signals to said programming inputs; and means, coupled between said power-on sense means and said logic means, for enabling said logic means responsive to said pulse signal.

Claim 13

The method of claim 9 further comprising the steps of: dividing said array into a logic portion containing a plurality of memory elements coupled to said output cell for normal operation of said circuit and an architecture portion containing said architecture element; disabling said logic portion of said array responsive to said power-on sense pulse; and enabling said architecture portion of said array responsive to said power-on sense pulse.