EP0284985A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1988-03-23
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Granted: —
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Expires: 2008-03-23
Abstract
Abstract A semiconductor memory device determines a level of a select control signal according to a level of drive signals for two systems as generated in the preceding access cycle, and a level of the least significant bit of an address to fetch data in a desired serial access cycle. According to this select signal, a select circuit (10) selects one of the drive signals as generated by drive signal generating circuits (55, 58), and supplies the selected signal to two data selecting/fetching systems (51, 52, 53, 54, 59, 60, 61, 62). The function of this select circuit allows one of the two data selecting/fetching systems (51, 52, 53, 54, 59, 60, 61, 62) to first start the data access operation.
Inventors
- 👤 Haruki C/O Patent Division Toda
- 👤 Hiroshi C/O Patent Division Sahara
- 👤 Shigeo C/O Patent Division Ohshima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 23:52
CPC Classifications
G; G11; G11C; G11C7/00; G11C8/00; G11C8/18; G11C7/10; G11C7/1006; G11C7/1015; G11C7/103; G11C8/06
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
85 words
A serially-accessed type memory device having two data selecting/fetching systems alternately operated for data fetching, characterized by drive signal generating circuits (56, 58) for generating first drive signals with different phases to control said data selecting/fetching systems (51, 52, 53, 54, 59, 60, 61, 62), according to serial access control signal; and a select circuit (10) for selecting one of said first drive signals and applying the selected first drive signal to said two data selecting/fetching systems (51, 52, 53, 54, 59, 60, 61, 62).
Claim 2
Dependent Claim
85 words
A serially-accessed type memory device having two data selecting/fetching systems alternately operated for data fetching, characterized by drive signal generating circuits (56, 58) for generating first drive signals with different phases to control said data selecting/fetching systems (51, 52, 53, 54, 59, 60, 61, 62), according to serial access control signal; and a select circuit (10) for selecting one of said first drive signals and applying the selected first drive signal to said two data selecting/fetching systems (51, 52, 53, 54, 59, 60, 61, 62).
Claim 3
Dependent Claim
79 words
The memory device according to claim 1, characterized in that said select circuit (10) is so arranged that when an address to fetch data in a desired serial access cycle for data fetching is designated, said select circuit selects one of said first drive signals according to a state of the least significant bit of said address, and a state of the second drive signals as generated by said drive signal generating circuit before said desired serial access cycle.
Claim 4
Dependent Claim
94 words
A serially-accessed type memory device having two data selecting/fetching systems alternately operated for data fetching, characterized by serial address generating circuits (55, 57) provided respectively in said two data selecting/fetching systems (51, 52, 53, 54, 59, 60, 61, 62), drive signal generating circuits (56, 58) for generating drive signals with different phases to be applied to said address generating circuits (55, 57) according to serial access control signal, and a select circuit (10) for selecting one of said first drive signals and applying the selected first drive signal to said two address generating circuits.
Claim 5
Dependent Claim
94 words
A serially-accessed type memory device having two data selecting/fetching systems alternately operated for data fetching, characterized by serial address generating circuits (55, 57) provided respectively in said two data selecting/fetching systems (51, 52, 53, 54, 59, 60, 61, 62), drive signal generating circuits (56, 58) for generating drive signals with different phases to be applied to said address generating circuits (55, 57) according to serial access control signal, and a select circuit (10) for selecting one of said first drive signals and applying the selected first drive signal to said two address generating circuits.
Claim 6
Dependent Claim
79 words
The memory device according to claim 3, characterized in that said select circuit (10) is so arranged that when an address to fetch data in a desired serial access cycle for data fetching is designated, said select circuit selects one of said first drive signals according to a state of the least significant bit of said address, and a state of the second drive signals as generated by said drive signal generating circuit before said desired serial access cycle.
References Cited (Backward Citations)
No citation records indexed.
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