US5703828A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-12-29
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Granted: 1997-12-30
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Expires: 2015-12-29
Abstract
Abstract A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
Inventors
- 👤 Churoo Park
- 👤 Hyun-Soon Jang
- 👤 Chull-Soo Kim
- 👤 Myung-Ho Kim
- 👤 Seung-Hun Lee
- 👤 Si-Yeol Lee
- 👤 Ho-Cheol Lee
- 👤 Tae-Jin Kim
- 👤 Yun-ho Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:19
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/40618; G11C11/4063; G11C11/407; G11C11/4076; G11C11/408; G11C11/4082; G11C11/4087; G11C7/1045; G11C7/1072; G11C7/22; G11C7/222; G11C7/225; G11C2207/00; G11C2207/22; G11C2207/2281
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
166 words
A dynamic random access memory comprising: a plurality of memory banks, each bank including a plurality of memory cells having addresses associated therewith and a separate address buffer for qenerating addresses and operable in one of an active cycle and a precharge cycle at any one time; first means for receiving a row address strobe signal and producing a first signal; second means for receiving a column address strobe signal and producing a second signal; third means for receiving a write enable signal and producing a third signal; address input means for receiving a portion of one of said addresses to indicate selection of one of said memory banks; and logic means, responsive to said first, second and third signals and said one address portion, for generating a separate row address strobe clock for each of said plurality of memory banks and allow for each memory bank to operate with overlapping active cycles using addresses from said separate address buffer associated with each said memory bank.
Claim 2
Dependent Claim
166 words
A dynamic random access memory comprising: a plurality of memory banks, each bank including a plurality of memory cells having addresses associated therewith and a separate address buffer for qenerating addresses and operable in one of an active cycle and a precharge cycle at any one time; first means for receiving a row address strobe signal and producing a first signal; second means for receiving a column address strobe signal and producing a second signal; third means for receiving a write enable signal and producing a third signal; address input means for receiving a portion of one of said addresses to indicate selection of one of said memory banks; and logic means, responsive to said first, second and third signals and said one address portion, for generating a separate row address strobe clock for each of said plurality of memory banks and allow for each memory bank to operate with overlapping active cycles using addresses from said separate address buffer associated with each said memory bank.
Claim 3
Dependent Claim
22 words
A semiconductor memory circuit according to claim 1 wherein said first and third signals are produced in synchronism with an external clock.
Claim 4
Dependent Claim
29 words
A semiconductor memory circuit according to claim 1 wherein said logic means detects a normal read operation mode and precharging of said plurality of memory banks takes place simultaneously.
Claim 5
Dependent Claim
22 words
A semiconductor memory circuit according to claim 3 wherein said first and third signals are produced in synchronism with an external clock.
Claim 6
Dependent Claim
60 words
A semiconductor memory circuit according to claim 1 wherein said logic means detects an interleave read operation mode and precharging of one of said memory banks takes place during a portion of a first active cycle that does not overlap with precharging of another of said memory banks during a first precharge cycle that overlaps with said first active cycle.
Claim 7
Dependent Claim
22 words
A semiconductor memory circuit according to claim 5 wherein said first and third signals are produced in synchronism with an external clock.
Claim 8
Dependent Claim
35 words
A semiconductor memory circuit according to claim 1 wherein each of said separate address buffers generate a different address for each of said banks when each of said banks are simultaneously in an active cycle.
Claim 9
Dependent Claim
175 words
A dynamic random access memory comprising: a plurality of memory banks, each bank including a plurality of memory cells having addresses associated therewith and a separate address buffer for generating addresses and operable in one of an active cycle and a precharge cycle at any one time; row address strobe input circuitry which receives a row address strobe signal and produces a first signal; column address strobe input circuitry which receives a column address strobe signal and produces a second signal; write enable input circuitry which receives a write enable signal and produces a third signal; an address input for receiving a portion of one of said addresses to indicate selection of one of said memory banks; and a logic circuit, responsive to said first, second and third signals and said one address portion, for generating a separate row address strobe clock for each of said plurality of memory banks and allow for each memory bank to operate with overlapping active cycles using addresses from said separate address buffer associated with each said memory bank.
Claim 10
Dependent Claim
175 words
A dynamic random access memory comprising: a plurality of memory banks, each bank including a plurality of memory cells having addresses associated therewith and a separate address buffer for generating addresses and operable in one of an active cycle and a precharge cycle at any one time; row address strobe input circuitry which receives a row address strobe signal and produces a first signal; column address strobe input circuitry which receives a column address strobe signal and produces a second signal; write enable input circuitry which receives a write enable signal and produces a third signal; an address input for receiving a portion of one of said addresses to indicate selection of one of said memory banks; and a logic circuit, responsive to said first, second and third signals and said one address portion, for generating a separate row address strobe clock for each of said plurality of memory banks and allow for each memory bank to operate with overlapping active cycles using addresses from said separate address buffer associated with each said memory bank.
Claim 11
Dependent Claim
22 words
A semiconductor memory circuit according to claim 8 wherein said first and third signals are produced in synchronism with an external clock.
Claim 12
Dependent Claim
29 words
A semiconductor memory circuit according to claim 8 wherein said logic circuit detects a normal read operation mode and precharging of said plurality of memory banks takes place simultaneously.
Claim 13
Dependent Claim
22 words
A semiconductor memory circuit according to claim 10 wherein said first and third signals are produced in synchronism with an external clock.
Claim 14
Dependent Claim
60 words
A semiconductor memory circuit according to claim 8 wherein said logic circuit detects an interleave read operation mode and precharging of one of said memory banks takes place during a portion of a first active cycle that does not overlap with precharging of another of said memory banks during a first precharge cycle that overlaps with said first active cycle.
Claim 15
Dependent Claim
22 words
A semiconductor memory circuit according to claim 12 wherein said first and third signals are produced in synchronism with an external clock.
Claim 16
Dependent Claim
35 words
A semiconductor memory circuit according to claim 8 wherein each of said separate address buffers generate a different address for each of said banks when each of said banks are simultaneously in an active cycle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-29 | 2001-06-30 | 2001-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-29 | 2005-06-30 | 2005-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-29 | 2009-06-30 | 2009-12-30 | $7700.00 | Window Closed / Lapsed |