US4833650A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device including programmable mode selection circuitry
Assignee: Mitsubishi Electric Corp
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Filing: 1987-04-02
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Granted: 1989-05-23
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Expires: 2007-04-02
Abstract
Abstract A semiconductor memory device includes a plurality of operation mode control circuits provided on a memory chip of the device for respectively executing a corresponding plurality of writing/reading operation modes including at least a static column mode, a high speed page mode and a nibble mode, and a plurality of operation mode selection circuits provided on the memory chip, each of the operation mode selection circuits having a fuse element and a bonding pad for selecting one of the plurality of the operation mode control circuits when the fuse element is cut off or the bonding pad is selectively wired, so that various functions can be selectively effected on the same chip.
Inventors
- 👤 Kazutoshi Hirayama
- 👤 Hideyuki Ozaki
- 👤 Kazuyasu Fujishima
- 👤 Hideto Hidaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:11
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/22; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C7/10; G11C7/1015; G11C7/103; G11C7/1033; G11C7/1045
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
151 words
A semiconductor memory device characterized by a plurality of operation mode control circuit means provided on a memory chip of said device for respectively executing a corresponding plurality of writing/reading operation modes including at least a static column mode, a high speed page mode and a nibble mode, and a plurality of operation mode selection circuit means provided on said memory chip and which can be programmed in accordance with a predetermined pattern, each of the plurality of operation mode selection circuit means having a fuse element for enabling activation of a selected one of said plurality of operation mode control circuit means when a corresponding fuse element is cut off and having a bonding pad for enabling activation of the selected operation mode control circuit when a corresponding bonding pad is wired to a predetermined reference terminal, said fuse element and bonding pad being selected on a mutually exclusive basis.
Claim 2
Dependent Claim
151 words
A semiconductor memory device characterized by a plurality of operation mode control circuit means provided on a memory chip of said device for respectively executing a corresponding plurality of writing/reading operation modes including at least a static column mode, a high speed page mode and a nibble mode, and a plurality of operation mode selection circuit means provided on said memory chip and which can be programmed in accordance with a predetermined pattern, each of the plurality of operation mode selection circuit means having a fuse element for enabling activation of a selected one of said plurality of operation mode control circuit means when a corresponding fuse element is cut off and having a bonding pad for enabling activation of the selected operation mode control circuit when a corresponding bonding pad is wired to a predetermined reference terminal, said fuse element and bonding pad being selected on a mutually exclusive basis.
Claim 3
Dependent Claim
32 words
A semiconductor memory device as set forth in claim 1, characterized in that each of said fuse elements can be cut off by a laser beam from an external laser trimmer apparatus.
Claim 4
Dependent Claim
31 words
A semiconductor memory device as set forth in claim 1, characterized in that each of said fuse elements can be cut off by an electric current from an external power source.
Claim 5
Dependent Claim
41 words
A semiconductor memory device as set forth in claim 1 wherein each of said operation mode selection circuit means further includes output circuit means for coupling an associated fuse element and bonding pad to a corresponding operation mode control circuit means.
Claim 6
Dependent Claim
46 words
A semiconductor memory device as set forth in claim 7 wherein each of said output circuit means comprises a logic circuit means for coupling a signal to a corresponding operation mode control circuit means either from an associated fuse element or from an associated bonding pad.
Claim 7
Dependent Claim
20 words
A semiconductor memory device as set forth in claim 5 wherein each of said output circuit means includes gate means.
Claim 8
Dependent Claim
45 words
A semiconductor memory device as set forth in claim 6 wherein each of said operation mode selection circuit means includes a first inverter having an input coupled to a corresponding bonding pad and a second inverter having an input coupled to a corresponding fuse element.
Claim 9
Dependent Claim
51 words
A semiconductor memory device as set forth in claim 7 wherein each of said logic circuit means comprises a NOR gate having one input coupled to the output of a corresponding first inverter and a second input coupled to the output of a corresponding second inverter, and including an output terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-22 | 1992-11-21 | 1993-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-22 | 1996-11-21 | 1997-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-22 | 2000-11-21 | 2001-05-23 | $7700.00 | Window Closed / Lapsed |