US4590388A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS spare decoder circuit
Assignee: Nokia Bell Labs
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Filing: 1984-04-23
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Granted: 1986-05-20
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Expires: 2004-04-23
Abstract
Abstract A spare decoder provides for the substitution of a spare component for repair of a defective semiconductor chip. For example, a spare row or column of memory cells can be substituted for a defective row or column of a memory chip by fusing fusible links in the decoder. The present invention implements the decoder in CMOS technology. To minimize power consumption, means are included for preventing current flow in an unused spare without having to fuse a link.
Inventors
- 👤 Donald G. Clemons
- 👤 Michael V. DePaolis, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:16
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/83
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
143 words
An integrated circuit comprising an array of field effect transistors capable of being programmed by fusing fusible means so that said array as programmed responds to a unique one of 2 n logic states, CHARACTERIZED IN THAT said array comprises a series string of n pairs of field effect transistors having a channel of a first conductivity type, wherein said fusible means are capable of changing each of said transistors between an operative and a nonoperative condition, wherein said string is adapted to carry a decoder current that flows through the channels of the operative transistors therein; and further charactered by additional fusible means for preventing the flow of said current until said additional fusible means is fused; and still further characterized by enabling means to allow said decoder current to flow only when an enabling signal is in a given voltage state.
Claim 2
Dependent Claim
143 words
An integrated circuit comprising an array of field effect transistors capable of being programmed by fusing fusible means so that said array as programmed responds to a unique one of 2 n logic states, CHARACTERIZED IN THAT said array comprises a series string of n pairs of field effect transistors having a channel of a first conductivity type, wherein said fusible means are capable of changing each of said transistors between an operative and a nonoperative condition, wherein said string is adapted to carry a decoder current that flows through the channels of the operative transistors therein; and further charactered by additional fusible means for preventing the flow of said current until said additional fusible means is fused; and still further characterized by enabling means to allow said decoder current to flow only when an enabling signal is in a given voltage state.
Claim 3
Dependent Claim
61 words
The integrated circuit of claim 1 wherein said array further comprises a parallel string of n pairs of field effect transistors having a channel of a second conductivity type opposite said first conductivity type, and wherein the channel currents flowing through the operative transistors in said parallel string are combined at a common node so as to produce said decoder current.
Claim 4
Dependent Claim
23 words
The integrated circuit of claim 1 wherein said additional fusible means is in the conducting state until the application of fusing energy thereto.
Claim 5
Dependent Claim
23 words
The integrated circuit of claim 1 wherein said additional fusible means is in the nonconducting state until the application of fusing energy thereto.
Claim 6
Dependent Claim
29 words
The integrated circuit of claim 1 wherein said additional fusible means is adapted to being changed between the conducting and the non-conducting state by the application of laser energy.
Claim 7
Dependent Claim
28 words
The integrated circuit of claim 1 wherein said additional means is adapted to being changed between the conducting and nonconducting state by the application of an electrical current.
Claim 8
Dependent Claim
27 words
The integrated circuit of claim 1 wherein said additional fusible means controls a voltage on the gate of a control transistor through which said decoder current flows.
Claim 9
Dependent Claim
32 words
The integrated circuit of claim 7 further comprising current limiting means to limit the current that flows through said additional fusible means when said enabling signal allows said decoder current to flow.
Claim 10
Dependent Claim
35 words
The integrated circuit of claim 7 wherein said additional fusible means controls the gate voltage of a complementary pair of field effect transistors, wherein said complementary pair controls the gate voltage of said control transistor.
Claim 11
Dependent Claim
27 words
The integrated circuit of claim 7 wherein said enabling signal controls the voltage on the gate of said control transistor when said additional fusible means is fused.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-19 | 1989-11-18 | 1990-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-19 | 1993-11-18 | 1994-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-19 | 1997-11-18 | 1998-05-20 | $7700.00 | Window Closed / Lapsed |