US4685084A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for selecting alternate addressing mode and read-only memory
Assignee: Intel Corp
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Filing: 1985-06-07
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Granted: 1987-08-04
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Expires: 2005-06-07
Abstract
Abstract An EPROM which includes on-chip circuitry for selecting alternate addressing. An EPROM cell, separate from the memory's array, is programmed to convert the memory to the alternate page mode addressing. The selection of the pages is done through the data lines. This frees address lines when the alternate mode is selected.
Inventors
- 👤 George R. Canepa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:51
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C17/00; G11C17/14; G11C17/18
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
115 words
In an integrated circuit, read-only memory having n address lines used for accessing p words in one addressing mode, an improvement for providing an alternate addressing mode, comprising: programmable selection means for selecting said alternate addressing mode; storage means for storing at least one signal; an address buffer coupled to one of said n address lines, said buffer also being coupled to said storage means and said programmable selection means, the output of said buffer being controlled by said signal stored in said storage means when said alternate addressing mode is selected, whereby when said alternate addressing mode is selected said p words in said memory may be selected with less than n address signals.
Claim 2
Dependent Claim
115 words
In an integrated circuit, read-only memory having n address lines used for accessing p words in one addressing mode, an improvement for providing an alternate addressing mode, comprising: programmable selection means for selecting said alternate addressing mode; storage means for storing at least one signal; an address buffer coupled to one of said n address lines, said buffer also being coupled to said storage means and said programmable selection means, the output of said buffer being controlled by said signal stored in said storage means when said alternate addressing mode is selected, whereby when said alternate addressing mode is selected said p words in said memory may be selected with less than n address signals.
Claim 3
Dependent Claim
19 words
The improvement defined by claim 1 wherein said storage means is coupled to a data terminal of said memory.
Claim 4
Dependent Claim
37 words
The improvement defined by claim 2 including an enabling means for enabling a signal on said data terminal to be stored in said storage means, said enabling means being coupled to one of said n address lines.
Claim 5
Dependent Claim
27 words
The improvement defined by claims 1 or 3 including a circuit for storing a predetermined signal in said storage means when power is applied to said memory.
Claim 6
Dependent Claim
18 words
The improvement defined by claim 4 wherein said programmable selection means comprises an electrically programmable read-only memory cell.
Claim 7
Dependent Claim
13 words
The improvement defined by claim 5 wherein said storage means comprises a latch.
Claim 8
Dependent Claim
129 words
In an integrated circuit electrically programmable read-only memory having n address lines used for accessing p words stored in said memory in one addressing mode, an improvement for providing an alternate addressing mode, comprising: an electrically programmable read-only memory cell for selecting said alternate addressing mode; storage means for storing signals, said storage means being coupled to data terminals of said memory; address buffers coupled to said address lines, said buffers also being coupled to said storage means and said memory cell such that the output of said buffers is controlled by said signals stored in said storage means when said alternate address mode is selected, whereby when said alternate addressing mode is selected said p words in said memory may be addressed with less than n address signals.
Claim 9
Dependent Claim
129 words
In an integrated circuit electrically programmable read-only memory having n address lines used for accessing p words stored in said memory in one addressing mode, an improvement for providing an alternate addressing mode, comprising: an electrically programmable read-only memory cell for selecting said alternate addressing mode; storage means for storing signals, said storage means being coupled to data terminals of said memory; address buffers coupled to said address lines, said buffers also being coupled to said storage means and said memory cell such that the output of said buffers is controlled by said signals stored in said storage means when said alternate address mode is selected, whereby when said alternate addressing mode is selected said p words in said memory may be addressed with less than n address signals.
Claim 10
Dependent Claim
35 words
The improvement defined by claim 7 including an enabling means for enabling storage of said signals in said storage means from said data terminals, said enabling means being coupled to one of said address lines.
Claim 11
Dependent Claim
24 words
The improvement defined by claim 8 including a circuit for storing predetermined signals in said storage means when power is applied to said memory.
Claim 12
Dependent Claim
12 words
The improvement defined by claim 9 wherein said storage means comprises latches.
References Cited (Backward Citations)
GB2101372A
Cited
US4594690A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-03 | 1991-02-02 | 1991-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-03 | 1995-02-02 | 1995-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-03 | 1999-02-02 | 1999-08-04 | $7700.00 | Window Closed / Lapsed |