Semiconductor memory device with page and nibble modes

Claim 1

A semiconductor memory device comprising: a memory cell array, comprising memory cells arranged in rows and columns to form a matrix; array control means for controlling the memory cell array and being operable in a page mode or a nibble mode, said array control means comprising a first CAS buffer circuit responsive to an external CAS signal for producing an internal CAS signal in synchronism with the external CAS signal, and a second CAS buffer circuit which comprises a mode selection means for selective connection for operation in the page mode or the nibble mode, and a NAND gate for receiving the output of the mode selection means and the external CAS signal to produce an internal CAS signal; and said mode selection means comprising: a selective voltage circuit comprising a first fuse, connected to produce a ground potential when the first fuse is unblown and producing a power source voltage (Vcc) when the first fuse is blown, and a MOS transistor receiving, at its gate, the output of said selective voltage circuit and having its drain connected to receive a first signal (φD) related to the internal CAS signal, and its source connected through a second fuse to the power source (Vcc), the source of the MOS transistor forming the output of the mode selection circuit.