US4446534A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable fuse circuit
Assignee: National Semiconductor Corp
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Filing: 1980-12-08
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Granted: 1984-05-01
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Expires: 2000-12-08
Abstract
Abstract A programmable fuse circuit has a fusable polysilicon element programmable in response to an "illegal" condition on existing pins of an integrated circuit. This programmable fuse circuit is incorporated in a programmable partial memory circuit, a reconfigurable format memory circuit, and a chip select circuit.
Inventors
- 👤 Frederick J. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:33
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
139 words
A programmable fuse circuit for providing a control signal on a control terminal comprising: means for providing a first voltage; means for providing a second voltage; means for providing an input signal; a first transistor having a first terminal coupled to the means for providing an input signal, a gate coupled to the means for providing the first voltage, and a second terminal; a first resistor coupled between the second terminal of the first transistor and the means for providing the first voltage; a second transistor having a first terminal coupled to the means for supplying the second voltage, a second terminal coupled to the control terminal, and a gate coupled to the second terminal of the first transistor; and a fuse coupled between the second terminal of the second transistor and the means for providing the first voltage.
Claim 2
Dependent Claim
139 words
A programmable fuse circuit for providing a control signal on a control terminal comprising: means for providing a first voltage; means for providing a second voltage; means for providing an input signal; a first transistor having a first terminal coupled to the means for providing an input signal, a gate coupled to the means for providing the first voltage, and a second terminal; a first resistor coupled between the second terminal of the first transistor and the means for providing the first voltage; a second transistor having a first terminal coupled to the means for supplying the second voltage, a second terminal coupled to the control terminal, and a gate coupled to the second terminal of the first transistor; and a fuse coupled between the second terminal of the second transistor and the means for providing the first voltage.
Claim 3
Dependent Claim
34 words
A programmable fuse circuit as in claim 1, further comprising a second resistor, having a resistance greater than the resistance of the fuse, coupled between the first and second terminals of the second transistor.
Claim 4
Dependent Claim
28 words
A programmable fuse circuit as in claim 1 or 2 wherein the fuse will permanently become an open circuit in response to current flow through the second transistor.
Claim 5
Dependent Claim
92 words
A method for programming a programmable fuse circuit as in claim 1 or 2 comprising the steps of: providing a ground voltage on the means for providing the second voltage; providing a slightly negative voltage on the means for providing the input signal; providing a positive voltage on the means for providing the first voltage; providing a positive voltage on the means for providing the input signal; providing a ground voltage on the means for providing the first voltage; and providing a positive voltage on the means for providing the second voltage.
Claim 6
Dependent Claim
194 words
A chip select circuit having a plurality of programmable fuse circuits, each programmable fuse circuit comprising: means for providing a first voltage; means for providing a second voltage; means for providing an input signal; a first transistor having a first terminal coupled to the means for providing an input signal, a gate coupled to the means for providing the first voltage, and a second terminal; a first resistor coupled between the second terminal and the first transistor and the means for providing a first voltage; a second transistor having a first terminal coupled to the means for supplying the second voltage, a second terminal coupled to the control terminal, and a gate coupled to the second terminal of the first transistor; and a fused coupled between the second terminal of the second transistor and the means for providing the first voltage; and further comprising a plurality of select terminals, one corresponding to each programmable fuse circuit, and compare means coupled to the programmable fuse circuits and to the select terminals for providing a chip select signal in response to signal on the input terminals matching the control signals of the corresponding programmable fuse circuits.
Claim 7
Dependent Claim
194 words
A chip select circuit having a plurality of programmable fuse circuits, each programmable fuse circuit comprising: means for providing a first voltage; means for providing a second voltage; means for providing an input signal; a first transistor having a first terminal coupled to the means for providing an input signal, a gate coupled to the means for providing the first voltage, and a second terminal; a first resistor coupled between the second terminal and the first transistor and the means for providing a first voltage; a second transistor having a first terminal coupled to the means for supplying the second voltage, a second terminal coupled to the control terminal, and a gate coupled to the second terminal of the first transistor; and a fused coupled between the second terminal of the second transistor and the means for providing the first voltage; and further comprising a plurality of select terminals, one corresponding to each programmable fuse circuit, and compare means coupled to the programmable fuse circuits and to the select terminals for providing a chip select signal in response to signal on the input terminals matching the control signals of the corresponding programmable fuse circuits.
Claim 8
Dependent Claim
67 words
A selectable memory circuit having a chip select circuit as in claim 5 for providing data signals on the data lines in response to data stored in memory elements in response to address signals applied to address lines and to a chip select signal having a first voltage level and for not providing data signals in response to the chip select signal having a second voltage level.
References Cited (Backward Citations)
US3845476A
Cited
US4122540A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-01 | 1987-10-31 | 1988-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-01 | 1991-10-31 | 1992-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-01 | 1995-10-31 | 1996-05-01 | $7700.00 | Window Closed / Lapsed |