US3845476A
Expired / Lapsed
US
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Monolithic memory using partially defective chips
Assignee: International Business Machines Corp
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Filing: 1972-12-29
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Granted: 1974-10-29
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Expires: 1992-12-29
Abstract
Abstract A monolithic memory which uses both good chips and partially defective chips. For a selected group of chips, for example those mounted on an array card, the defects are limited to the same sector of each chip. When an address signal corresponds to the address of the defective chip sector, logic circuitry translates the address signal to an address at an all-good chip. The data is then written into or read out of the good chip sector instead of a defective chip sector. Provision of a programmable circuit on each array card allows sets of chips, each set having defects in a different sector, to be mounted on different array cards, thereby insuring profitable usage of substantially all partially defective chips.
Inventors
- 👤 R Boehm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 04:43
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
86 words
A monolithic memory comprising: a plurality of nondefective integrated circuit chips; a plurality of partially defective integrated circuit chips, each having one or more defects in the same predetermined sector thereof; each of said chips having an array of memory cells therein; each of said memory cells having a respective address assigned thereto; input means for signals addressing said cells; and means for converting the address signals corresponding to those cells in said defective sectors to new address signals corresponding to locations in said non-defective chips.
Claim 2
Dependent Claim
86 words
A monolithic memory comprising: a plurality of nondefective integrated circuit chips; a plurality of partially defective integrated circuit chips, each having one or more defects in the same predetermined sector thereof; each of said chips having an array of memory cells therein; each of said memory cells having a respective address assigned thereto; input means for signals addressing said cells; and means for converting the address signals corresponding to those cells in said defective sectors to new address signals corresponding to locations in said non-defective chips.
Claim 3
Dependent Claim
49 words
A monolithic memory as in claim 1 wherein said converting means comprises: logic circuitry having inputs for signals corresponding to the addresses of the cells in the defective sectors of the partially defective chips and outputs for signals corresponding to the addresses of the cells in the non-defective chips.
Claim 4
Dependent Claim
76 words
A monolithic memory as in claim 2 wherein said logic circuitry comprises: decision means responsive to certain ones of said addressing signals for signaling when a defective sector has been addressed; means responsive to a signal from said decision means for selecting said plurality of non-defective chips when a defective sector has been addressed; and translation means for translating the address of said defective sector to an address of an associated sector in a non-defective chip.
Claim 5
Dependent Claim
51 words
A monolithic memory as in claim 3 further comprising: programmable means connected between said translation means and the chips for assuring that said certain ones of said addressing signals correspond to the address of a defective sector, irrespective of which one of the sectors in the partially defective chips is defective.
Claim 6
Dependent Claim
101 words
A monolithic memory comprising: a plurality of integrated circuit chips, each of said chips having an array of memory cells divided into N sectors; a particular one of said N sectors in each chip having defective cells; said plurality of defective chips being an integral multiple of N; a single non-defective chip for each N defective chips; each of said memory cells having a respective address assigned thereto; input means for signals addressing said cells; and means for converting the address signals corresponding to those cells in said defective sectors to new address signals corresponding to location in said non-defective chips.
Claim 7
Dependent Claim
101 words
A monolithic memory comprising: a plurality of integrated circuit chips, each of said chips having an array of memory cells divided into N sectors; a particular one of said N sectors in each chip having defective cells; said plurality of defective chips being an integral multiple of N; a single non-defective chip for each N defective chips; each of said memory cells having a respective address assigned thereto; input means for signals addressing said cells; and means for converting the address signals corresponding to those cells in said defective sectors to new address signals corresponding to location in said non-defective chips.
Claim 8
Dependent Claim
84 words
A monolithic memory comprising: at least one storage card having mounted thereon a first set of nondefective integrated circuIt chips and eight sets of integrated circuit chips having chips with defects only in the same respective octant of each chip; each of said chips having an array of memory cells therein; each of said memory cells having a respective address assigned thereto; and means for converting the addresses of cells in said defective octants to addresses of cells in said first set of chips.
Claim 9
Dependent Claim
84 words
A monolithic memory comprising: at least one storage card having mounted thereon a first set of nondefective integrated circuIt chips and eight sets of integrated circuit chips having chips with defects only in the same respective octant of each chip; each of said chips having an array of memory cells therein; each of said memory cells having a respective address assigned thereto; and means for converting the addresses of cells in said defective octants to addresses of cells in said first set of chips.
Claim 10
Dependent Claim
97 words
A monolithic memory comprised of at least one storage card, each card having mounted thereon: a plurality of non-defective integrated circuit chips; a plurality of partially defective integrated circuit chips, each having one or more defects in the same predetermined sector thereof; each of said chips having an array of memory cells therein; each of said memory cells having a respective address assigned thereto; input means for signals addressing said cells; and means for converting the address signals corresponding to those cells in said defective sectors to new address signals corresponding to locations in said non-defective chips.
Claim 11
Dependent Claim
97 words
A monolithic memory comprised of at least one storage card, each card having mounted thereon: a plurality of non-defective integrated circuit chips; a plurality of partially defective integrated circuit chips, each having one or more defects in the same predetermined sector thereof; each of said chips having an array of memory cells therein; each of said memory cells having a respective address assigned thereto; input means for signals addressing said cells; and means for converting the address signals corresponding to those cells in said defective sectors to new address signals corresponding to locations in said non-defective chips.
Claim 12
Dependent Claim
49 words
A monolithic memory as in claim 7 wherein said converting means comprises: logic circuitry having inputs for signals corresponding to the addresses of the cells in the defective sectors of the partially defective chips and outputs for signals corresponding to the addresses of the cells in the non-defective chips.
Claim 13
Dependent Claim
76 words
A monolithic memory as in claim 8 wherein said logic circuitry comprises: decision means responsive to certain ones of said addressing signals for signaling when a defective sector has been addressed; means responsive to a signal from said decision means for selecting said plurality of non-defective chips when a defective sector has been addressed; and translation means for translating the address of said defective sector to an address of an associated sector in a non-defective chip.
Claim 14
Dependent Claim
51 words
A monolithic memory as in claim 9 further comprising: programmable means connected between said translation means and the chips for assuring that said certain ones of said addressing signals correspond to the address of a defective sector, irrespective of which one of the sectors in the partially defective chips is defective.
Claim 15
Dependent Claim
19 words
A monolithic memory as in claim 7 wherein said predetermined sector is different on different ones of said cards.
Claim 16
Dependent Claim
42 words
A monolithic memory as in claim 11 further comprising: programmable means for assuring that the same address signals from said input means correspond to the address of a defective sector, irrespective of which one of the sectors on said cards is defective.
Claim 17
Dependent Claim
36 words
A monolithic memory as in claim 7 wherein at least one card has mounted thereon a plurality of non-defective chips only and said at least one card has mounted thereon: means for deactivating said converting means.
Claim 18
Independent Claim
88 words
A method of making a monolithic memory of the type containing a plurality of integrated circuit chips, each having an array of memory cells therein, comprising the steps of: testing said chips to determine which cells thereof are defective; sorting said tested chips into a first sort having all-good cells and other sorts having defective cells in respective sectors of the chips; and assembling said chips onto cards with a predetermined number of said first sort and predetermined number of one of the other sorts on a card.
Claim 19
Independent Claim
88 words
A method of making a monolithic memory of the type containing a plurality of integrated circuit chips, each having an array of memory cells therein, comprising the steps of: testing said chips to determine which cells thereof are defective; sorting said tested chips into a first sort having all-good cells and other sorts having defective cells in respective sectors of the chips; and assembling said chips onto cards with a predetermined number of said first sort and predetermined number of one of the other sorts on a card.
Claim 20
Independent Claim
89 words
A method of making a monolithic memory of the type containing a plurality of integrated circuit chips, each having an array of memory cells therein, comprising the steps of: testing said chips to determine which cells are defective; sorting said tested chips into a first sort having all-good cells and eight other sorts having defective cells only in a respective octant of the chips; and assembling said chips onto cards, each card containing a single set of said first sort and eight sets of one of the other sorts.
Claim 21
Independent Claim
89 words
A method of making a monolithic memory of the type containing a plurality of integrated circuit chips, each having an array of memory cells therein, comprising the steps of: testing said chips to determine which cells are defective; sorting said tested chips into a first sort having all-good cells and eight other sorts having defective cells only in a respective octant of the chips; and assembling said chips onto cards, each card containing a single set of said first sort and eight sets of one of the other sorts.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-28 | 1978-04-29 | 1978-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-28 | 1982-04-29 | 1982-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-28 | 1986-04-29 | 1986-10-29 | $7700.00 | Window Closed / Lapsed |