US3715735A
Expired / Lapsed
US
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Segmentized memory module and method of making same
Assignee: Advanced Micro Devices Inc
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Filing: 1970-12-14
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Granted: 1973-02-06
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Expires: 1990-12-14
Abstract
Abstract A method of utilizing a memory array or module containing inoperative memory cells or bits is accomplished by electrically segmentizing the memory module and then permanently isolating the segment(s) containing inoperative bits to form a segmentized but functional memory module. This is accomplished by forcing the address means associated with the segment(s) containing inoperative bits to a permanent, single binary state which is inconsistent with the binary address codes for the memory cells in the segment(s) containing the inoperative bits.
Inventors
- 👤 W Moss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 04:42
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
86 words
A memory array containing a matrix of memory circuits, and wherein said array includes inoperative circuits, comprising; a. means for electrically segmentizing said memory array into M sub-arrays by providing N address bits to said memory array, where M 2N; b. means for identifying sub-arrays containing inoperative bits; and c. means for permanently isolating 2N 1 sub-arrays including those sub-arrays containing inoperative bits by permanently maintaining the address bits associated with said sub-arrays at a single binary signal level inconsistent with the operation of said sub-arrays.
Claim 2
Dependent Claim
86 words
A memory array containing a matrix of memory circuits, and wherein said array includes inoperative circuits, comprising; a. means for electrically segmentizing said memory array into M sub-arrays by providing N address bits to said memory array, where M 2N; b. means for identifying sub-arrays containing inoperative bits; and c. means for permanently isolating 2N 1 sub-arrays including those sub-arrays containing inoperative bits by permanently maintaining the address bits associated with said sub-arrays at a single binary signal level inconsistent with the operation of said sub-arrays.
Claim 3
Dependent Claim
142 words
An operational memory module comprising a matrix of memory cells and at least one word line linking each row of memory cells, a pair of bit lines linking each column of memory cells, means associated with said word lines and said bit lines for selectively enabling any desired memory cell in said module, each of said cells being addressed by a unique combination of binary coded signals, and wherein the improvement comprises: means for segmentizing said memory module into M equal sub-modules by providing N address signals thereto, where M 2N; means for permanently driving 2N 1 of said sub-modules into a single continuous binary state incompatible with the binary address codes associated with the memory cells associated with said sub-modules, said 2N 1 sub-modules containing sub-modules having inoperative bits; and means for utilizing the remaining sub-modules as an operative memory module.
Claim 4
Dependent Claim
142 words
An operational memory module comprising a matrix of memory cells and at least one word line linking each row of memory cells, a pair of bit lines linking each column of memory cells, means associated with said word lines and said bit lines for selectively enabling any desired memory cell in said module, each of said cells being addressed by a unique combination of binary coded signals, and wherein the improvement comprises: means for segmentizing said memory module into M equal sub-modules by providing N address signals thereto, where M 2N; means for permanently driving 2N 1 of said sub-modules into a single continuous binary state incompatible with the binary address codes associated with the memory cells associated with said sub-modules, said 2N 1 sub-modules containing sub-modules having inoperative bits; and means for utilizing the remaining sub-modules as an operative memory module.
Claim 5
Dependent Claim
44 words
The memory module of claim 2 wherein said address means includes decoder means associated with each of said word lines and each of said pair of bit lines and wherein said driving means includes means for driving selected word line and bit line decoders.
Claim 6
Dependent Claim
15 words
The memory module of claim 2 wherein N is 1 and M is therefore 2.
Claim 7
Dependent Claim
15 words
The memory module of claim 2 wherein N is 2 and M is therefore 4.
Claim 8
Dependent Claim
15 words
The memory module of claim 2 wherein N is 3 and M is therefore 8.
Claim 9
Dependent Claim
145 words
In a memory module having a matrix of memory cells having at least one word line linking each row of memory cells and a pair of bit lines linking each column Of memory cells, and wherein said memory module additionally includes address means associated with said word lines and said bit lines for selectively enabling any desired memory cell in said module, each of said cells being addressed by a unique combination of binary coded signals, wherein the invention comprises the method of segmentizing said memory module into M equal sub-modules by providing N address signals thereto, where M 2N; permanently driving 2N 1 of said sub-modules into a single continuous binary state incompatible with the binary address codes associated with the memory cells associated with said sub-modules, said 2N 1 sub-modules containing sub-modules having inoperative bits; and utilizing the remaining sub-modules containing operative bits.
Claim 10
Dependent Claim
145 words
In a memory module having a matrix of memory cells having at least one word line linking each row of memory cells and a pair of bit lines linking each column Of memory cells, and wherein said memory module additionally includes address means associated with said word lines and said bit lines for selectively enabling any desired memory cell in said module, each of said cells being addressed by a unique combination of binary coded signals, wherein the invention comprises the method of segmentizing said memory module into M equal sub-modules by providing N address signals thereto, where M 2N; permanently driving 2N 1 of said sub-modules into a single continuous binary state incompatible with the binary address codes associated with the memory cells associated with said sub-modules, said 2N 1 sub-modules containing sub-modules having inoperative bits; and utilizing the remaining sub-modules containing operative bits.
Claim 11
Dependent Claim
48 words
The method of claim 7 wherein said address means includes decoder means associated with each of said word lines and each of said pair of bit lines and wherein said step of driving said portion of said address means comprises driving selected word line and bit line decoders.
Claim 12
Dependent Claim
14 words
The method of claim 7 wherein N is 1 and M is therefore 2.
Claim 13
Dependent Claim
14 words
The method of claim 7 wherein N is 2 and M is therefore 4.
Claim 14
Dependent Claim
14 words
The method of claim 7 wherein N is 3 and M is therefore 8.
Claim 15
Independent Claim
64 words
A method of electrically segmentizing a memory module to eliminate segments containing inoperative bits comprising permanently addressing 2N 1 of 2N equal segments of bits of the memory module including those segments containing inoperative bits therein with a continuous signal of a single binary state, said latter binary state being incompatible with the address codes associated with the bits of said 2N 1 segments.
Claim 16
Independent Claim
64 words
A method of electrically segmentizing a memory module to eliminate segments containing inoperative bits comprising permanently addressing 2N 1 of 2N equal segments of bits of the memory module including those segments containing inoperative bits therein with a continuous signal of a single binary state, said latter binary state being incompatible with the address codes associated with the bits of said 2N 1 segments.
Claim 17
Independent Claim
86 words
A method of utilizing a memory array containing a matrix of memory circuits and wherein said array includes inoperative circuits, comprising the steps of: a. segmentizing said memory array into M sub-arrays by providing N address bits to said memory array, where M 2N; b. locating sub-arrays containing inoperative memory circuits; c. electrically isolating 2N 1 sub-arrays including those sub-arrays containing inoperative bits by permanently maintaining the address bits associated with said sub-arrays at a single binary signal level inconsistent with the operation of said sub-arrays.
Claim 18
Independent Claim
86 words
A method of utilizing a memory array containing a matrix of memory circuits and wherein said array includes inoperative circuits, comprising the steps of: a. segmentizing said memory array into M sub-arrays by providing N address bits to said memory array, where M 2N; b. locating sub-arrays containing inoperative memory circuits; c. electrically isolating 2N 1 sub-arrays including those sub-arrays containing inoperative bits by permanently maintaining the address bits associated with said sub-arrays at a single binary signal level inconsistent with the operation of said sub-arrays.
Claim 19
Dependent Claim
13 words
The method of claim 13 wherein N is one and M is two.
Claim 20
Dependent Claim
13 words
The method of claim 13 wherein N is two and M is four.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-06 | 1976-08-07 | 1977-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-06 | 1980-08-07 | 1981-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-06 | 1984-08-07 | 1985-02-06 | $7700.00 | Window Closed / Lapsed |