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US5440260A Expired / Lapsed US ⏱️ 0.0 years remaining

Variable delay circuit

Assignee: Advantest Corp
•
Filing: 1994-06-02
•
Granted: 1995-08-08
•
Expires: 2014-06-02
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Abstract

Abstract The gate of a CMOS transistor formed by a series connection of p-channel and n-channel FETs 21 and 22 is connected to an input terminal 23, and the drain of the CMOS transistor is connected to an output terminal 24. The source of the FET 21 is connected to a positive power supply terminal 20 via parallel-connected switchable resistance elements 37 0 , 37 1 , 37 2 , . . formed by p-channel FETs and having resistance values R 0 , R 1 , R 2 , . . . , respectively. The source of the other FET 22 is connected to a negative power supply terminal 30 via parallel-connected switchable resistance elements 38 0 , 38 1 , 38 2 , . . . formed by n-channel FETs and having resistance values R 0 , R 1 , R 2 , . . . , respectively. Delay setting signals S 0 , S 1 , . . . are decoded by a decoder 39 and one of more of its output terminals Y 0 , Y 1 , . . . go to the high level. The output terminals Y 0 , Y 1 , Y 2 , . . . are connected directly to the gates of the FETs forming the resistance elements 38 0 , 38 1 , 38 2 , . . . , respectively, and are connected to the gates of the FETs of the resistance elements 37 0 , 37 1 , 37 2 , . . . via inverters. The time constant of the charge and discharge for a load capacitance at the output terminal 24 differs with combinations of two resistance elements which are simultaneously turned ON, changing a delay of the input signal accordingly.

Inventors

  • 👤 Yokichi Hayashi
  • 👤 Hiroshi Tsukahara
  • 👤 Katsumi Ochiai
  • 👤 Mashuhiro Yamada
  • 👤 Naoyoshi Watanabe

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 16:40
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; H03K17/00; H03K17/16; H03K17/161; H03K17/162; H03K17/163; H03K5/133

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 264 words
A fine variable delay circuit comprising: a CMOS transistor having two series-connected FETs of different conductivity types, said two FETs having their gates connected together to a signal input terminal and having their drains connected together to a signal output terminal; a first FET connected between one of said two FETs of said CMOS transistor and one end of a power supply and having the same conductivity type as that of said one FET; a second FET connected between the other FET of said CMOS transistor and the other end of said power supply and having the same conductivity type as that of said other FET, said first and second FETs having their gates connected to said signal input terminal; a third FET connected between the connection point of said CMOS transistor and said first FET and the other end of said power supply and having the same conductivity type as that of said first FET, said third FET having its gate connected to said output end of said CMOS transistor; a fourth FET connected between the connection point of said CMOS transistor and said second FET and said one end of said power supply and having the same conductivity as that of said second FET, said fourth FET having its gate connected to said output end of said CMOS transistor; a first switch connected in series to said third FET; a second switch connected in series to said fourth FET; and delay setting means responsive to a select signal to control said gates of said third and fourth FETs, thereby setting a delay.
Claim 2
Dependent Claim 264 words
A fine variable delay circuit comprising: a CMOS transistor having two series-connected FETs of different conductivity types, said two FETs having their gates connected together to a signal input terminal and having their drains connected together to a signal output terminal; a first FET connected between one of said two FETs of said CMOS transistor and one end of a power supply and having the same conductivity type as that of said one FET; a second FET connected between the other FET of said CMOS transistor and the other end of said power supply and having the same conductivity type as that of said other FET, said first and second FETs having their gates connected to said signal input terminal; a third FET connected between the connection point of said CMOS transistor and said first FET and the other end of said power supply and having the same conductivity type as that of said first FET, said third FET having its gate connected to said output end of said CMOS transistor; a fourth FET connected between the connection point of said CMOS transistor and said second FET and said one end of said power supply and having the same conductivity as that of said second FET, said fourth FET having its gate connected to said output end of said CMOS transistor; a first switch connected in series to said third FET; a second switch connected in series to said fourth FET; and delay setting means responsive to a select signal to control said gates of said third and fourth FETs, thereby setting a delay.
Claim 3
Dependent Claim 283 words
The fine variable delay circuit of claim 1, further comprising a CMOS transistor having two series-connected FETs of different conductivity types, said two FETs having their gates connected together to form an input end of said CMOS transistor and having their drains connected to form an output end of said CMOS transistor; a first FET connected between one of said two FETs of said CMOS transistor and one end of a power supply and having the same conductivity type as that of said one FET; a second FET connected between the other FET of said CMOS transistor and the other end of said power supply and having the same conductivity type as that of said other FET; a third FET connected between said CMOS transistor and said first FET and said other end of said power supply and having the same conductivity type as that of said first FET, said third FET having its gate connected to said output end of said CMOS transistor; a fourth FET connected between the connection point of said CMOS transistor and said second FET and said one end of said power supply and having the same conductivity type as that of said second FET, said fourth FET having its gate connected to said output end of said CMOS transistor; a first switch connected in series to said third FET; a second switch connected in series to said fourth FET; wherein said input end and output end of said CMOS transistor are connected between said connection point of said first and second transistors and said delay output terminal, and said first and second switches are simultaneously set to the ON or OFF state by said delay setting means.

References Cited (Backward Citations)

US5055706A Cited
US5012142A Cited
US5051630A Cited
US5164621A Cited
US5121014A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-08-07 1999-02-06 1999-08-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-08-07 2003-02-06 2003-08-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-08-07 2007-02-06 2007-08-08 $7700.00 Window Closed / Lapsed

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