US5055706A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Delay circuit that resets after pulse-like noise
Assignee: Toshiba Corp
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Filing: 1989-02-17
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Granted: 1991-10-08
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Expires: 2009-02-17
Abstract
Abstract A semiconductor integrated circuit including delay means for generating an output signal delayed by a predetermined time with respect to an input signal when a logic level of said input signal changes in a first direction. The delay means receives a control signal and generates an internal control signal which is delayed by a predetermined time with respect to the control signal when a logic level of the control signal changes in a first direction, including a capacitor for delaying the control signal and a resistor having one end and having the other end connected to the capacitor.
Inventors
- 👤 Hiroto Nakai
- 👤 Hiroshi Iwahashi
- 👤 Masamichi Asano
- 👤 Shigeru Kumagai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:55
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/26; H03K; H03K5/00; H03K5/13; H03K5/133; H03K5/125; H03K5/1252; H03K2005/00013; H03K2005/0015; H03K2005/00195
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
216 words
A semiconductor integrated circuit for transmitting a signal from an input terminal to an output terminal providing a predetermined stable delay for one level transition of said input signal and no delay for the other level transition of said input signal, comprising: said input terminal for receiving said input signal and said output terminal for generating an output signal; a first inverter having an input terminal connected to said input terminal of said integrated circuit and having an output terminal; a second inverter having an input terminal connected to said output terminal of said first inverter means and having an output terminal; a first NAND gate having a first input terminal connected to said output terminal of said second inverter, a second input terminal connected to said input terminal of said integrated circuit, and an output terminal; a NOR gate having a first input terminal connected to said output terminal of said inverter, a second input terminal connected to said output terminal of said first NAND gate, and an output terminal; and a second NAND gate having a first input terminal connected to said input terminal of said integrated circuit, a second input terminal connected to said output terminal of said NOR gate, and an output terminal connected to said output terminal of said integrated circuit.
Claim 2
Dependent Claim
216 words
A semiconductor integrated circuit for transmitting a signal from an input terminal to an output terminal providing a predetermined stable delay for one level transition of said input signal and no delay for the other level transition of said input signal, comprising: said input terminal for receiving said input signal and said output terminal for generating an output signal; a first inverter having an input terminal connected to said input terminal of said integrated circuit and having an output terminal; a second inverter having an input terminal connected to said output terminal of said first inverter means and having an output terminal; a first NAND gate having a first input terminal connected to said output terminal of said second inverter, a second input terminal connected to said input terminal of said integrated circuit, and an output terminal; a NOR gate having a first input terminal connected to said output terminal of said inverter, a second input terminal connected to said output terminal of said first NAND gate, and an output terminal; and a second NAND gate having a first input terminal connected to said input terminal of said integrated circuit, a second input terminal connected to said output terminal of said NOR gate, and an output terminal connected to said output terminal of said integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-07 | 1995-04-08 | 1995-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-07 | 1999-04-08 | 1999-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-07 | 2003-04-08 | 2003-10-08 | $7700.00 | Window Closed / Lapsed |