CMOS power-on reset pulse generating circuit with extended reset pulse duration

Claim 1

A source voltage buildup detecting circuit which detects, after a source voltage is switched on, whether the source voltage is higher than a predetermined voltage and outputs a detecting signal accordingly, said source voltage buildup detecting circuit comprising: a complementary metal-oxide semiconductor (CMOS) inverter having a threshold voltage and an input terminal and providing an output signal; a level shifting element comprising one of a MOS transistor and a diode, operatively connected between the source voltage and said CMOS inverter; and a voltage generating circuit, operatively connected to the input terminal of said CMOS inverter, said level shifting element supplying a voltage lower than the source voltage to said CMOS inverter as a working voltage, when the source voltage becomes lower than the predetermined voltage after the source voltage is switched on, said voltage generating circuit outputs a voltage higher than the threshold voltage of said CMOS inverter, when the source voltage becomes higher than the predetermined voltage, said voltage generating circuit outputs a voltage lower than the threshold voltage of said CMOS inverter, and when the source voltage reaches the predetermined value, the output signal of said CMOS inverter is inverted.