US4140930A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage detection circuit composed of at least two MOS transistors
Assignee: Sharp Corp
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Filing: 1977-07-29
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Granted: 1979-02-20
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Expires: 1997-07-29
Abstract
Abstract A voltage level detection circuit comprises a first MOS transistor having the gate and the drain connected together with a power source voltage V DD via a resistor and the source grounded and a second MOS transistor having the gate connected with the drain of the first MOS transistor and the source grounded via a resistor. The circuit functions to compare the power source voltage V DD with a sum of the threshold voltage levels of the first and second MOS transistors, whereby voltage detection outputs are developed at the source of the second MOS transistor.
Inventors
- 👤 Shinichi Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:20
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/30; H03K17/302; G; G01; G01R; G01R19/00; G01R19/165; G01R19/16504; G01R19/16519; G01R19/16533; G01R19/16538
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
91 words
A voltage level detection and switching circuit comprising: a first MOS transistor; a second MOS transistor; a power source providing a source voltage; means for comparing the source voltage with the sum of the threshold voltage levels of said first and second MOS transistors; a flip-flop coupled to said comparison means, the output of said flip-flop being utilized as an initial condition setting signal; means for setting or resetting said flip-flop when the power source voltage exceeds the sum of the threshold voltage levels of said first and second MOS transistors.
Claim 2
Dependent Claim
91 words
A voltage level detection and switching circuit comprising: a first MOS transistor; a second MOS transistor; a power source providing a source voltage; means for comparing the source voltage with the sum of the threshold voltage levels of said first and second MOS transistors; a flip-flop coupled to said comparison means, the output of said flip-flop being utilized as an initial condition setting signal; means for setting or resetting said flip-flop when the power source voltage exceeds the sum of the threshold voltage levels of said first and second MOS transistors.
Claim 3
Dependent Claim
83 words
A circuit in accordance with claim 1, wherein said comparison means comprises: means connecting the gate and drain of said first MOS transistor together; a resistor connected between said power source and the drain of said first MOS transistor; means for connecting the source of said first MOS transistor to ground; means for connecting the gate of said second MOS transistor with the drain of said first MOS transistor; and means for grounding the drain of said second MOS transistor via a resistor.
Claim 4
Dependent Claim
21 words
A circuit means in accordance with claim 2, wherein said resetting means comprises a P-channel transistor responsive to a reset signal.
Claim 5
Dependent Claim
97 words
A circuit in accordance with claim 1, wherein said comparison means comprises: means for connecting the gate and the drain of said first MOS transistor together; two resistors connected in series between the power source and the drain of said first MOS transistors; means for grounding the source of said first MOS transistor; means for connecting the gate of said second MOS transistor to a junction between said two series resistors in the drain circuit of said first MOS transistor; and means for connecting the drain of said second MOS transistor to ground via a third transistor.
Claim 6
Dependent Claim
21 words
A circuit means in accordance with claim 4, wherein said resetting means comprises a P-channel transistor responsive to a reset signal.
Claim 7
Dependent Claim
95 words
A circuit in accordance with claim 1, wherein said comparison means comprises: means for connecting the gate and the drain of said first MOS transistor together; two transistors in series connected between the drain of said first MOS transistor and said power source; means for connecting the source of said first MOS transistor ground; means for connecting the gate of said second MOS transistor to a junction between said two series transistors in the drain circuit of said first MOS transistor; and transistor means for connecting the drain of said second MOS transistor to ground.
Claim 8
Dependent Claim
21 words
A circuit means in accordance with claim 6, wherein said resetting means comprises a P-channel transistor responsive to a reset signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-02-19 | 1982-08-21 | 1983-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-02-19 | 1986-08-21 | 1987-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-02-19 | 1990-08-21 | 1991-02-20 | $7700.00 | Window Closed / Lapsed |