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US4045688A Expired / Lapsed US ⏱️ 0.0 years remaining

Power-on reset circuit

Assignee: RCA Corp
•
Filing: 1976-10-26
•
Granted: 1977-08-30
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Expires: 1996-10-26
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Abstract

Abstract The circuit includes a MOS transistor for transmitting the applied voltage wave to the output signal terminal during the interval that the applied voltage is between two voltage limits and circuit elements responsive to the applied voltage wave exceeding the higher of these limits for disabling the MOS transistor and for clamping the output signal terminal to a reference level such as ground. The circuit elements include a pair of complementary MOS transistors connected such that the higher voltage limit is a value slightly higher than the highest of their respective threshold voltages but which may be less than the sum thereof.

Inventors

  • 👤 Roger Green Stewart

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 07:29
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 192 words
In a switching circuit of the kind comprising a first threshold circuit responsive to an input voltage for producing at its output terminal an output voltage corresponding to that portion of said input voltage of greater than a given magnitude, a second threshold circuit having a threshold higher than the first threshold circuit and responsive also to said input voltage for clamping said output terminal to a point of reference voltage when said input voltage exceeds the threshold of said second threshold circuit and feedback means responsive to signals present on said output terminal for providing a control signal to said first threshold circuit for inactivating said first threshold circuit when said output terminal is clamped to said point of reference voltage, the improvement for inactivating said second threshold circuit subsequent to the inactivation of said first threshold circuit, comprising: switch means coupled between said output terminal and said point of reference potential and responsive to said control signal for closing when said control signal is present; and means in said second threshold circuit responsive also to said control signal for disabling said second threshold circuit when said control signal is present.
Claim 2
Dependent Claim 192 words
In a switching circuit of the kind comprising a first threshold circuit responsive to an input voltage for producing at its output terminal an output voltage corresponding to that portion of said input voltage of greater than a given magnitude, a second threshold circuit having a threshold higher than the first threshold circuit and responsive also to said input voltage for clamping said output terminal to a point of reference voltage when said input voltage exceeds the threshold of said second threshold circuit and feedback means responsive to signals present on said output terminal for providing a control signal to said first threshold circuit for inactivating said first threshold circuit when said output terminal is clamped to said point of reference voltage, the improvement for inactivating said second threshold circuit subsequent to the inactivation of said first threshold circuit, comprising: switch means coupled between said output terminal and said point of reference potential and responsive to said control signal for closing when said control signal is present; and means in said second threshold circuit responsive also to said control signal for disabling said second threshold circuit when said control signal is present.
Claim 3
Dependent Claim 53 words
The switching circuit recited in claim 1 wherein said switch means comprises a field effect transistor having a conduction path and a control electrode, said conduction path being connected between said output terminal and said point of reference voltage, said control electrode being coupled to said feedback means for receiving said control signal.
Claim 4
Dependent Claim 92 words
The switching circuit recited in claim 1 wherein said second threshold circuit comprises first and second complementary field effect transistors, the drain and source electrodes of the first being connected, respectively, to said output terminal and said point of reference voltage, the gate electrode of the first being connected to the drain electrode of the second, the source electrode of the second for receiving said input voltage and wherein said means for disabling said second threshold circuit comprises means for applying said control signal to the gate electrode of said second transistor.
Claim 5
Dependent Claim 110 words
The switching circuit recited in claim 1 wherein said second threshold circuit comprises first and second field effect transistors of a first conductivity type and a third field effect transistor of a second conductivity type, the source electrodes of the first and second transistors being connected to said point of reference potential, the drain electrode of the first transistor being connected to said output terminal, the gate electrode of the first transistor and the drain electrodes of the second and third transistors being connected together thereby forming a circuit node, and means for applying said input voltage to the source and gate electrodes, repectively, of said third and second transistors.
Claim 6
Dependent Claim 21 words
The switching circuit recited in claim 4 further comprising capacitor means coupled between said node and said point of reference voltage.
Claim 7
Dependent Claim 154 words
A power-on reset circuit comprising: first, second and third P-channel field effect transistors and fourth, fifth, sixth, and seventh N-channel field effect transistors, each transistor having a source electrode, a gate electrode and a drain electrode; an input terminal connected to the source electrodes of said first, second and third transistors and to the gate electrode of said seventh transistor; a common terminal connected to the source electrodes of said fourth, fifth, sixth and seventh transistors; an output terminal connected to the gate electrodes of said first and fourth transistors and to the drain electrodes of said second, fifth and sixth transistors; a first circuit node connected to the drain electrodes of said first and fourth transistors and to the gate electrodes of said second, third and fifth transistors; and a second circuit node connected to the gate electrode of said sixth transistor and to the drain electrodes of said third and seventh transistors.
Claim 8
Dependent Claim 154 words
A power-on reset circuit comprising: first, second and third P-channel field effect transistors and fourth, fifth, sixth, and seventh N-channel field effect transistors, each transistor having a source electrode, a gate electrode and a drain electrode; an input terminal connected to the source electrodes of said first, second and third transistors and to the gate electrode of said seventh transistor; a common terminal connected to the source electrodes of said fourth, fifth, sixth and seventh transistors; an output terminal connected to the gate electrodes of said first and fourth transistors and to the drain electrodes of said second, fifth and sixth transistors; a first circuit node connected to the drain electrodes of said first and fourth transistors and to the gate electrodes of said second, third and fifth transistors; and a second circuit node connected to the gate electrode of said sixth transistor and to the drain electrodes of said third and seventh transistors.
Claim 9
Dependent Claim 45 words
The circuit recited in claim 6 further comprising: first capacitor means connected between said input terminal and said output terminal; second capacitor means connected between said first node and said common terminal; and third capacitor means connected between said second node and said common terminal.

References Cited (Backward Citations)

US3823551A Cited
US3809926A Cited
US3899690A Cited
US3851189A Cited
US3894247A Cited
US3895239A Cited
US4001609A Cited
US3950654A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-08-29 1981-02-28 1981-08-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-08-29 1985-02-28 1985-08-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-08-29 1989-02-28 1989-08-30 $7700.00 Window Closed / Lapsed

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