US3851189A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bisitable digital circuitry
Assignee: Raytheon Co
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Filing: 1973-06-25
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Granted: 1974-11-26
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Expires: 1993-06-25
Abstract
Abstract Bistable digital circuits including cross coupled gates having complementary inputs provided by CMOS threshold circuits coupled to a common digital signal input. Complementary unbalanced transfer characteristics of the threshold circuits provide widely separated high and threshold voltages approaching respective high and low supply potentials. The coupling between gates maintains the bistable digital circuits in a given stable state until the high and low threshold voltages are crossed over in response to a change in logical level at the signal input.
Inventors
- 👤 N Moyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:35
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/01; H03K3/013; H03K3/02; H03K3/353; H03K3/356; H03K3/3565
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
111 words
Logical storage means comprising: complementary threshold circuit means including a pair of complementary MOS inverter circuits having inputs for receiving digital signals, and outputs; said threshold circuit means having unbalanced transfer characteristics providing separated high and low threshold levels near high and low supply potentials, respectively, bistable circuit means having a plurality of inputs coupled to said threshold circuit outputs for receiving complementary high and low logical level input signals to provide a stable state condition, said bistable state circuit means including outputs for providing high and low level logical signals indicating the stable state of the bistable circuit means, and said bistable circuit means comprises NOR gates having crosscoupled outputs.
Claim 2
Dependent Claim
111 words
Logical storage means comprising: complementary threshold circuit means including a pair of complementary MOS inverter circuits having inputs for receiving digital signals, and outputs; said threshold circuit means having unbalanced transfer characteristics providing separated high and low threshold levels near high and low supply potentials, respectively, bistable circuit means having a plurality of inputs coupled to said threshold circuit outputs for receiving complementary high and low logical level input signals to provide a stable state condition, said bistable state circuit means including outputs for providing high and low level logical signals indicating the stable state of the bistable circuit means, and said bistable circuit means comprises NOR gates having crosscoupled outputs.
Claim 3
Dependent Claim
42 words
The logical storage means of claim 1 which further includes an inverter circuit coupling the threshold circuit means to said bistable circuit means to provide complementary high and low level logical stable state signals to the inputs of the bistable circuit means.
Claim 4
Dependent Claim
63 words
The logical storage means according to claim 1 in which said complementary MOS circuits include relatively high and low impedance P-channel and N-channel devices respectively to provide an unbalanced transfer characteristic and a low threshold voltage near the low supply potential and relatively low and high impedance P-channel and N-channel devices respectively to provide a high threshold voltage near the high supply potential.
Claim 5
Dependent Claim
100 words
The logical storage means according to claim 1, wherein a signal input circuit means for supplying said complementary input signals is connected to said plurality of inputs, said signal input means comprising a complementary pair of threshold circuits having separated high and low threshold levels responding to changes in the logical level of an input signal traversing said threshold levels, said bistable circuit means including circuit means for maintaining one of the stable states and responsive to a combination of changes in logical levels of the complementary input signals to produce a change in state of said bistable circuit means.
Claim 6
Dependent Claim
107 words
Logical storage means comprising: complementary threshold circuit means including a pair of complementary MOS inverter circuits having inputs for receiving digital signals, and outputs; said threshold circuit means having unbalanced transfer characteristics providing separated high and low threshold levels near high and low supply potentials, respectively; bistable circuit means having inputs coupled to said threshold circuit outputs for receiving complementary high and low logical level signals to provide a stable state condition, said bistable state circuit means including outputs for providing high and low level logical signals indicating the stable state of the bistable circuit means; and said bistable circuit means comprises NAND gates having cross-coupled outputs.
Claim 7
Dependent Claim
107 words
Logical storage means comprising: complementary threshold circuit means including a pair of complementary MOS inverter circuits having inputs for receiving digital signals, and outputs; said threshold circuit means having unbalanced transfer characteristics providing separated high and low threshold levels near high and low supply potentials, respectively; bistable circuit means having inputs coupled to said threshold circuit outputs for receiving complementary high and low logical level signals to provide a stable state condition, said bistable state circuit means including outputs for providing high and low level logical signals indicating the stable state of the bistable circuit means; and said bistable circuit means comprises NAND gates having cross-coupled outputs.
Claim 8
Dependent Claim
100 words
The logical storage means according to claim 5, wherein a signal input circuit means for supplying said complementary input signals is connected to said plurality of inputs, said signal input means comprising a complementary pair of threshold circuits having separated high and low threshold levels responding to changes in the logical level of an input signal traversing said threshold levels, said bistable circuit means including circuit means for maintaining one of the stable states and responsive to a combination of changes in logical levels of the complementary input signals to produce a change in state of said bistable circuit means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-25 | 1978-05-27 | 1978-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-25 | 1982-05-27 | 1982-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-25 | 1986-05-27 | 1986-11-26 | $7700.00 | Window Closed / Lapsed |