Circuit for initalizing logic following power turn on

Claim 2

A power initialization circuit comprising in combination: first and second charging circuit means each having an input terminal and an output terminal, said first and second charging circuit means producing first and second time delays, respectively, following the application of a predetermined voltage to the input terminals of said charging circuit means; first inverter means having an input terminal and an output terminal, said input terminal of said inverter means connected to said output terminal of said second charging circuit means for inverting the logical value of the signal produced by said second charging circuit means; latch means having first and second input terminals and at least a first output terminal, said first input terminal connected to the output terminal of said first charging circuit means and the second input terminal of said latch means connected to said output terminal of said first inverter means for providing an output signal at the end of the longer of the first and second time delay periods.

Claim 3

The combination recited in claim 1 including source means for selectively supplying a signal to both said first and second charging circuit means; each of said first and second charging circuit means including an RC circuit and a fast discharge shunt path.

Claim 4

The combination recited in claim 1 wherein the delay period of said second time delay means is at least 10 times longer than the delay Period of said first time delay means to assure that the input signal at the first input terminal of said latch means changes before the input signal at the second input terminal of said latch means changes.

Claim 5

A power initialization circuit comprising, in combination: first and second time delay means for producing first and second time delays, respectively; latch means having first and second input terminals and first and second output terminals, said first input terminal connected to the first time delay means, said second input terminal connected to said second time delay means, for providing an output signal at the end of the longer of the two time delay periods; first one shot pulse generating means having an input terminal and an output terminal, said input terminal of said first one shot pulse generating means connected to said first output terminal of said latch means for generating one pulse in response to a predetermined change in the output signal of said first output terminal of said latch means; system initialization means having an input terminal connected to the output terminal of said first one shot pulse generating means, said system initialization circuit means controlling the application of a reset signal to a circuit the resetting of which is delayed from the initial application of power to the system in accordance with the input signal supplied to said system initialization means; second one shot pulse generating means having an input terminal and an output terminal, said input terminal of said second one shot pulse generating means connected to the output terminal of said first one shot pulse generating means for producing one pulse at the output of said second one shot pulse generating means in response to a predetermined change in the output signal of said first one shot pulse generating means; gate means having first and second input terminals and an output terminal, said first input terminal of said gate means connected to the second output terminal of said latch means and said second input terminal of said gate means connected to the output terminal of said second one shot pulse generating means, said gate means producing a first signal at the output terminal thereof in response to the application of prescribed signals to said first and second input terminals of said gate means; and program initialization means having an input terminal connected to the output terminal of said gate means for initializing a program when said first signal is produced at said output terminal of said gate means.

Claim 6

A power initialization circuit comprising, in combination: first and second time delay means for producing first and second time delays, respectively; latch means having first and second input terminals and first and second output terminals, said first input terminal connected to the first time delay means, said second input terminal connected to said second time delay means, for providing an output signal at the end of the longer of the two time delay periods; first one shot pulse generating means having an input terminal and an output terminal, said input terminal of said first one shot pulse generating means connected to said first output terminal of said latch means for generating one pulse in response to a predetermined change in the output signal of said first output terminal of said latch means; system initialization means having an input terminal connected to the output terminal of said first one shot pulse generating means, said system initialization circuit means controlling the application of a reset signal to a circuit the resetting of which is delayed from the initial application of power to the system in accordance with the input signal supplied to said system initialization means; second one shot pulse generating means having an input terminal and an output terminal, said input terminal of said second one shot pulse generating means connected to the output terminal of said first one shot pulse generating means for producing one pulse at the output of said second one shot pulse generating means in response to a predetermined change in the output signal of said first one shot pulse generating means; gate means having first and second input terminals and an output terminal, said first input terminal of said gate means connected to the second output terminal of said latch means and said second input terminal of said gate means connected to the output terminal of said second one shot pulse generating means, said gate means producing a first signal at the output terminal thereof in response to the application of prescribed signals to said first and second input terminals of said gate means; and program initialization means having an input terminal connected to the output terminal of said gate means for initializing a program when said first signal is produced at said output terminal of said gate means.

Claim 7

The combination recited in claim 4 further comprising: inverter means connected in series between said gate means and said program initialization means, said inverter means having an input terminal and an output terminal, said input terminal of said inverter means connected to the output terminal of said gate means and the output terminal of said inverter means connected to the input terminal of said program initialization means.

Claim 8

A power initialization circuit comprising, in combination: first and second time delay means for producing first and second time delays, respectively; latch means having first and second input terminals and at least a first output terminal, said first input terminal connected to the first time delay means, said second input terminal connected to said second time delay means, for providing an output signal at the end of the longer of the two time delay periods; first one shot pulse generating means having an input terminal and an output terminal, said input terminal of said first one shot pulse generating means connected to said first output terminal of said latch means for generating one pulse in response to a predetermined change in the output signal of said first output terminal of said latch means; system initialization means having an input terminal connected to the output terminal of said first one shot pulse generating means, said system initializatIon circuit means controlling the application of a reset signal to a circuit the resetting of which is delayed from the initial application of power to the system in accordance with the input signal supplied to said system initialization means; first inverter means connected in series between said second time delay means and said second input terminal of said latch means, said first inverter means have an input terminal and an output terminal, said input terminal of said inverter means connected to said second time delay means for inverting the logical value of the signal produced by said second time delay means, and said output terminal of said first inverter means connected to the second input terminal of said latch means; second inverter means connected in series between said first one shot pulse generating means and said system initialization means, said second inverter means having an input terminal and an output terminal, said input terminal of said second inverter means connected to the output terminal of said first one shot pulse generating means and the output terminal of said second inverter means connected to the input terminal of said system initialization means.

Claim 9

A power initialization circuit comprising, in combination: first and second time delay means for producing first and second time delays, respectively; latch means having first and second input terminals and at least a first output terminal, said first input terminal connected to the first time delay means, said second input terminal connected to said second time delay means, for providing an output signal at the end of the longer of the two time delay periods; first one shot pulse generating means having an input terminal and an output terminal, said input terminal of said first one shot pulse generating means connected to said first output terminal of said latch means for generating one pulse in response to a predetermined change in the output signal of said first output terminal of said latch means; system initialization means having an input terminal connected to the output terminal of said first one shot pulse generating means, said system initializatIon circuit means controlling the application of a reset signal to a circuit the resetting of which is delayed from the initial application of power to the system in accordance with the input signal supplied to said system initialization means; first inverter means connected in series between said second time delay means and said second input terminal of said latch means, said first inverter means have an input terminal and an output terminal, said input terminal of said inverter means connected to said second time delay means for inverting the logical value of the signal produced by said second time delay means, and said output terminal of said first inverter means connected to the second input terminal of said latch means; second inverter means connected in series between said first one shot pulse generating means and said system initialization means, said second inverter means having an input terminal and an output terminal, said input terminal of said second inverter means connected to the output terminal of said first one shot pulse generating means and the output terminal of said second inverter means connected to the input terminal of said system initialization means.