Flip-flop circuit with a delay between a logical input circuit and the flip-flop

Claim 1

A FLIP-FLOP CIRCUIT ARRANGEMENT COMPRISING: FLIP-FLOP CIRCUIT MEANS INCLUDING A FIRST TRANSISTOR AND A SECOND TRANSISTOR; LOGICAL INPUT CIRCUIT MEANS HAVING A SINGLE LOGICAL INPUT AND FIRST AND SECOND OUTPUTS, SAID LOGICAL INPUT CIRCUIT MEANS BEING RESPONSIVE TO LOGICAL SIGNALS COUPLED TO SAID SINGLE INPUT CIRCUIT TO PRODUCE COMPLEMENTARY HIGH AND LOW LEVEL LOGICAL SIGNALS AT SAID FIRST AND SECOND OUTPUTS; A SOURCE OF GATING PULSES; AND FIRST AND SECOND GATING CIRCUIT MEANS COUPLED TO SAID FIRST AND SECOND TRANSISTORS, RESPECTIVELY EACH OF SAID GATING CIRCUIT MEANS INCLUDING A DELAY LINE AND A LOGICAL GATE, SAID DELAY LINE HAVING AN INPUT COUPLED TO A RESPECTIVE ONE OF SAID FIRST AND SECOND OUTPUTS FOR DELAYING A RESPECTIVE ONE OF THE COMPLEMENTARY LOGICAL SIGNALS, SAID LOGICAL GATE HAVING AN OUTPUT COUPLED TO A RESPECTIVE ONE OF SAID TRANSISTORS, A LOGICAL INPUT COUPLED TO THE OUTPUT OF THE RESPECTIVE DELAY LINE AND A GATING PULSE INPUT COUPLED TO SAID SOURCE OF GATING PULSES, SAID LOGICAL GATE BEING RESPONSIVE TO A DELAYED HIGH LEVEL LOGICAL SIGNAL COUPLED THERETO AND A GATING PULSE TO PRODUCE A TRIGGERING SIGNAL AT THE RESPECTIVE FIRST TRANSISTOR OR SECOND TRANSISTOR FOR PLACING THE FLIP-FLOP INTO A STATE CORRESPONDING TO THE LOGICAL SIGNAL COUPLED TO THE SINGLE INPUT CIRCUIT PRIOR TO THE GATING PULSE.