CMOS Reset circuit

Claim 2

A CMOS integrated power-on reset circuit for providing an output signal in response to the application of a voltage across a supply terminal and a reference terminal; the circuit comprising: a first circuit comprising a first capacitor having a first terminal and a second terminal, a first N-channel transistor having a drain coupled to the second terminal of the first capacitor, a source coupled to the reference terminal, and a gate, and first circuit means including a forward-biased diode coupled between the supply and reference terminals in series circuit with the gate and source of the first N-channel transistor; a second circuit comprising a second capacitor having a first terminal coupled to the reference terminal and a second terminal, a first P-channel transistor having a drain coupled to the second terminal of the second capacitor, a source coupled to the supply terminal, and a gate, and second circuit means including a forward-biased diode coupled between the supply and reference terminals in series circuit with the source of the first P-channel transistor; inverter means comprising a second P-channel transistor coupled in series circuit with a second N-channel transistor between the supply and reference terminals, the gates of the second transistors coupled, for providing the output signal in response to the voltage applied to the gates of the second transistors; wherein the second terminal of the capacitor of one of the first and second circuits is coupled to the gate of the transistor of the other of the first and second circuits and the second terminal of the capacitor of the other circuit is coupled to the gates of the second transistors.

Claim 3

A CMOS integrated power-on reset circuit as in claim 1 further comprising a back-biased first diode coupled between the second terminal of the first capacitor and the supply terminal and a back-biased second diode coupled between the second terminal of the second capacitor and the supply terminal.

Claim 4

A CMOS integrated power-on reset circuit as in claim 2 wherein the forward-biased diode of the first circuit means comprises a forward-biased third diode having an anode coupled to the supply terminal, a cathode coupled to the gate of the first N-channel transistor, and impedance means coupled between the cathode of the forward-biased third diode and the reference terminal for providing a current path therebetween.

Claim 5

A CMOS integrated power-on reset circuit as in claim 3 wherein the forward-biased diode of the second circuit means comprises a forward-biased fourth diode having an anode coupled to the supply terminal and a cathode coupled to the source of the first P-channel transistor.

Claim 6

A CMOS integrated power-on reset circuit as in claim 4 wherein the second terminal of the first capacitor is coupled to the gate of the first P-channel transistor and the second terminal of the second capacitor is coupled to the gates of the second transistors.

Claim 7

A CMOS integrated power-on reset circuit as in claim 5 wherein the impedance means comprises a third N-channel transistor having a gate coupled to the drains of the second P-channel and N-channel transistors, a drain coupled to the cathode of the third diode, and a source coupled to the reference terminal, the circuit further comprising a back-biased fifth diode coupled between the cathode of the third diode and the supply terminal.

Claim 8

A CMOS integrated power-on reset circuit as in claim 6 wherein the voltage drop across the forward-biased fourth diode is less than the threshold voltage of the second P-channel transistor.

Claim 9

A CMOS integrated power-on reset circuit for providing an output signal in response to the application of a voltage across a supply terminal and a reference terminal, the circuit comprising: a first circuit comprising a first first capacitor having a first terminal coupled to the supply terminal and a second terminal, a first N-channel transistor having a drain couple to the second terminal of the first capacitor, a source coupled to the reference terminal, and a a second circuit comprising a second capacitor having a first terminal coupled to the reference terminal and second terminal, a first P-channel transistor having a drain coupled to the second terminal of the second capacitor, a source coupled to the supply terminal, and a gate; inverter means comprising a second P-channel transistor coupled in series with a second N-channel transistor between the supply and reference terminals, the gates of the second transistors coupled, for providing the output signal in response to the voltage applied to the gates of the second transistors; wherein the second terminal of the capacitor of one of the first and second circuits is coupled to the gate of the transistor of the other of the first and second circuits and the second terminal of the capacitor of the other circuit is coupled to the gates of the second transistors; further comprising a forward biased diode having an anode coupled to the supply terminal and a cathode coupled to the source of the first P-channel transistor, the gate of the first P-channel transistor coupled to the reference terminal, the second terminal of the second capacitor coupled to the gate of the first N-channel transistor, and the second terminal of the first capacitor coupled to the gates of the second transistors.

Claim 10

A CMOS integrated power-on reset circuit for providing an output signal in response to the application of a voltage across a supply terminal and a reference terminal, the circuit comprising: a first circuit comprising a first first capacitor having a first terminal coupled to the supply terminal and a second terminal, a first N-channel transistor having a drain couple to the second terminal of the first capacitor, a source coupled to the reference terminal, and a a second circuit comprising a second capacitor having a first terminal coupled to the reference terminal and second terminal, a first P-channel transistor having a drain coupled to the second terminal of the second capacitor, a source coupled to the supply terminal, and a gate; inverter means comprising a second P-channel transistor coupled in series with a second N-channel transistor between the supply and reference terminals, the gates of the second transistors coupled, for providing the output signal in response to the voltage applied to the gates of the second transistors; wherein the second terminal of the capacitor of one of the first and second circuits is coupled to the gate of the transistor of the other of the first and second circuits and the second terminal of the capacitor of the other circuit is coupled to the gates of the second transistors; further comprising a forward biased diode having an anode coupled to the supply terminal and a cathode coupled to the source of the first P-channel transistor, the gate of the first P-channel transistor coupled to the reference terminal, the second terminal of the second capacitor coupled to the gate of the first N-channel transistor, and the second terminal of the first capacitor coupled to the gates of the second transistors.

Claim 11

A CMOS integrated power-on reset circuit as in claim 8 wherein the voltage drop across the forward-biased diode is less than the threshold voltage of the second P-channel transistor.

Claim 12

A CMOS integrated power on reset circuit for providing an output signal in response to the application of a voltage across a supply terminal and a reference terminal, the circuit comprising: a first voltage reference circuit coupled between said supply and said reference terminal, including a first MOSFET and a first diode connected thereto for establishing a first threshold voltage; a second voltage reference circuit coupled between said supply and said reference terminal and a terminal of said first voltage reference circuit and including a second MOSFET of complementary type of said first MOSFET and a second diode connected thereto for establishing a second threshold voltage; a CMOS inverter circuit connected to the output of said second voltage reference circuit and providing the output of said reset circuit in response to said supply terminal voltage exceeding the higher of said first or second threshold voltage.

Claim 13

A CMOS integrated power on reset circuit for providing an output signal in response to the application of a voltage across a supply terminal and a reference terminal, the circuit comprising: a first voltage reference circuit coupled between said supply and said reference terminal, including a first MOSFET and a first diode connected thereto for establishing a first threshold voltage; a second voltage reference circuit coupled between said supply and said reference terminal and a terminal of said first voltage reference circuit and including a second MOSFET of complementary type of said first MOSFET and a second diode connected thereto for establishing a second threshold voltage; a CMOS inverter circuit connected to the output of said second voltage reference circuit and providing the output of said reset circuit in response to said supply terminal voltage exceeding the higher of said first or second threshold voltage.

Claim 14

A CMOS power on reset circuit as claimed in claim 10 wherein the gate of said second MOSFET is coupled to a terminal of said first MOSFET, said first MOSFET terminal carrying a voltage which is responsive to the voltage on the gate of said first MOSFET.