Abnormal voltage detection circuit

Claim 2

An abnormal voltage detection circuit comprising first and second power source terminals; a integration circuit coupled between said first and second power source terminals; an inversion circuit having an input terminal connected to the output terminal of said integration circuit; and means for detecting a voltage interrupt at said source terminals comprising flip-flop means, connected to receive at a first input terminal thereof an output signal from said inversion circuit, for being set into a first condition indicating abnormal voltage upon resumption of interrupted voltage to said source terminals in response to a predetermined absolute voltage lower than the absolute threshold voltage of said inversion circuit and for remaining set even after said threshold voltage of said inversion circuit is surpassed.

Claim 3

An abnormal voltage detection circuit according to claim 1 wherein said flip-flop circuit is formed of an R-S flip-flop circuit having a set input terminal coupled to the output terminal of said inversion circuit and a reset input terminal coupled to a power source through a switch.

Claim 4

An abnormal voltage detection circuit according to claim 2, wherein said flip-flop circuit is composed of a plurality of IG FET's.

Claim 5

An abnormal voltage detection circuit according to claim 2, wherein said flip-flop circuit is composed of a plurality of CMOS FET's.

Claim 6

An abnormal voltage detection circuit according to claim 1, wherein said integration circuit is formed of a series circuit of a resistive means and a capacitor, and produces an output signal from the junction of said resistive means and capacitor.

Claim 7

An abnormal voltage detection circuit according to claim 5, wherein said resistive means is composed of a field effect transistor.

Claim 8

An abnormal voltage detection circuit according to claim 1, wherein said inversion circuit is formed of a series circuit of a resistive means and a field effect transistor coupled between said first and second power source terminals.

Claim 9

An abnormal voltage detection circuit according to claim 7, wherein said resistive means is composed of a field effect transistor.

Claim 10

The detector circuit of claim 1 further including resetting means for independently resetting said flip-flop means upon said resumption of interrupt voltage with said flip-flop remaining reset only upon said power source terminals surpassing said higher absolute threshold voltage of said inversion circuit.

Claim 11

An abnormal voltage detection circuit comprising first and second power source terminals; an integration circuit coupled between said first and second terminals; an inversion circuit having an input terminal connected to the output terminal of said integration circuit, said inversion circuit having a first threshold voltage; and a flip-flop circuit constituted by first and second field effect transistors whose current paths are connected in parallel to each other, the gate terminal of said first field effect transistor being connected to the output terminal of said inversion circuit, first resistive means connected in series with said first field effect transistor, third and fourth field effect transistors whose current paths are connected in parallel to each other, the gate terminal of said third field effect transistor being connected to the junction between said first resistive means and said first field effect transistor, second resistive means connected in series with said fourth field effect transistor, the junction between said second resistive means and fourth field effect transistor being connected to the gate terminal of said second field effect transistor; and switching means connected to the gate terminal of said fourth field effect transistor, said first and second field effect transistors being formed to have a threshold voltage lower than said first threshold voltage of said inversion circuit and said third and fourth field effect transistors being formed to have a threshold voltage higher than said first threshold voltage of said inversion circuit.

Claim 12

An abnormal voltage detection circuit comprising first and second power source terminals; an integration circuit coupled between said first and second terminals; an inversion circuit having an input terminal connected to the output terminal of said integration circuit, said inversion circuit having a first threshold voltage; and a flip-flop circuit constituted by first and second field effect transistors whose current paths are connected in parallel to each other, the gate terminal of said first field effect transistor being connected to the output terminal of said inversion circuit, first resistive means connected in series with said first field effect transistor, third and fourth field effect transistors whose current paths are connected in parallel to each other, the gate terminal of said third field effect transistor being connected to the junction between said first resistive means and said first field effect transistor, second resistive means connected in series with said fourth field effect transistor, the junction between said second resistive means and fourth field effect transistor being connected to the gate terminal of said second field effect transistor; and switching means connected to the gate terminal of said fourth field effect transistor, said first and second field effect transistors being formed to have a threshold voltage lower than said first threshold voltage of said inversion circuit and said third and fourth field effect transistors being formed to have a threshold voltage higher than said first threshold voltage of said inversion circuit.

Claim 13

An abnormal voltage detection circuit according to claim 10, wherein said first resistive means is formed of a fifth field effect transistor whose gate terminal is connected to the junction between said first and fifth field effect transistors, and said second resistive means is formed of a sixth field effect transistor whose gate terminal is connected to the junction between said fourth and sixth field effect transistors.

Claim 14

An abnormal voltage detection circuit according to claim 10, wherein said inversion circuit is formed of a third resistive means and a field effect transistor whose gate terminal is connected to the output terminal of said integration circuit and whose current path is connected in series with said third resistive means.

Claim 15

An abnormal voltage detection circuit according to claim 11, wherein said inversion circuit is formed of a third resistive means and a field effect transistor whose gate terminal is connected to the output terminal of said integration circuit and whose current path is connected in series with said third resistive means.

Claim 16

An abnormal voltage detection circuit comprising an integration circuit; an inversion circuit having an input terminal connected to the output terminal of said integration circuit, said inversion circuit having a first threshold voltage; and a flip-flop circuit constituted by first and second field effect transistors of a first channel type whose current paths are connected in parallel to each other, third and fourth field effect transistors of a second channel type different from said first channel type, the current path of said fourth field effect transistor being connected in series with said first field effect transistor through said third field effect transistor and the gate terminals of said first and third field effect transistors being connected to the output terminal of said inversion circuit, fifth and sixth field effect transistors of the first channel type whose current paths are connected in parallel to each other, seventh and eighth field effect transistors of the second channel type, the current path of said eighth field effect transistor being connected in series with said sixth field effect transistor through said seventh field effect transistor, the gate terminals of said fifth and eighth field effect transistors being connected to the junction of said first and third field effect transistors, and the junction between said fifth and seventh field effect transistors being connected to the gate terminals of said second and fourth transistors; and switching means connected to the gate terminals of said sixth and seventh field effect transistors, a series circuit of said first, third and fourth field effect transistors and a series circuit of said second, third and fourth field effect transistors being formed to have a threshold voltage lower than the first threshold voltage of said inversion circuit and a series circuit of said fifth, seventh and eighth field effect transistors and a series circuit of said sixth, seventh and eighth field effect transistors being formed to have a threshold voltage higher than the first threshold voltage of said inversion circuit.

Claim 17

An abnormal voltage detection circuit comprising an integration circuit; an inversion circuit having an input terminal connected to the output terminal of said integration circuit, said inversion circuit having a first threshold voltage; and a flip-flop circuit constituted by first and second field effect transistors of a first channel type whose current paths are connected in parallel to each other, third and fourth field effect transistors of a second channel type different from said first channel type, the current path of said fourth field effect transistor being connected in series with said first field effect transistor through said third field effect transistor and the gate terminals of said first and third field effect transistors being connected to the output terminal of said inversion circuit, fifth and sixth field effect transistors of the first channel type whose current paths are connected in parallel to each other, seventh and eighth field effect transistors of the second channel type, the current path of said eighth field effect transistor being connected in series with said sixth field effect transistor through said seventh field effect transistor, the gate terminals of said fifth and eighth field effect transistors being connected to the junction of said first and third field effect transistors, and the junction between said fifth and seventh field effect transistors being connected to the gate terminals of said second and fourth transistors; and switching means connected to the gate terminals of said sixth and seventh field effect transistors, a series circuit of said first, third and fourth field effect transistors and a series circuit of said second, third and fourth field effect transistors being formed to have a threshold voltage lower than the first threshold voltage of said inversion circuit and a series circuit of said fifth, seventh and eighth field effect transistors and a series circuit of said sixth, seventh and eighth field effect transistors being formed to have a threshold voltage higher than the first threshold voltage of said inversion circuit.

Claim 18

An abnormal voltage detection circuit according to claim 14, wherein said inversion circuit is formed of a ninth field effect transistor of the first channel type and a tenth field effect transistor of the second channel type whose current path is connected in series with said ninth field effect transistor and whose gate terminal is connected to the output terminal of said integration circuit together with the gate terminal of said ninth field effect transistor.